Fabrication of High Quality Capacitors by Impurity Enhanced Oxidation

Abstract

Effects of arsenic implant dose, energy, and annealing on (100) silicon have been investigated in order to develop a polycide/oxide/silicon capacitor structure for insertion into an established 1 μm CMOS process. Implantation of selected active areas produces a heavily doped silicon bottom plate on which a 500Å capacitor dielectric can be grown simultaneously with a 225Å gate oxide. Implant energies of 100 and 150 keV, arsenic doses of to , and a variety of annealing schedules were examined for their affect on 800° and 900°C (dry‐wet‐dry) oxidations in a 4.5% ambient. Aluminum top plate (MIS) and polycide top plate (SIS) capacitors were fabricated on enhanced oxides for electrical evaluation. Parameters were selected to obtain an SIS structure with a high specific capacitance of 68 nf/cm2, a low voltage coefficient (<50 ppm/V), and oxide uniformity comparable to that of the gate oxide.