Low-voltage CMOS Technology Research Articles

A Prototype System With Custom-Designed RX ICs for Contrast-Enhanced Ultrasound Imaging

This work presents a prototype system based on a multichannel receiving (RX) integrated circuit (IC) for contrast-enhanced ultrasound (CEUS) imaging. The RX IC is implemented in a 40-nm low-voltage CMOS technology and is designed to interface to a capacitive micromachined ultrasonic transducer array. To enable a direct connection of the RX electronics to the transducer, an analog multiplexer with on-chip protection circuitry is developed. Stress tests confirm the reliability of this arrangement when combined with a high-voltage pulser. The RX IC is equipped with a highly programmable bandpass filter to capture harmonic signals from ultrasound contrast agents (UCAs) while suppressing fundamental components. In order to examine the impact of analog front-end (AFE) bandpass filtering, in vitro acoustic experiments are performed with UCAs. A spatial resolution analysis suggests that the AFE bandpass filtering combined with a pulse inversion (PI) technique can improve the lateral resolution by 38% or 9% compared to the original full-bandwidth approach or a stand-alone PI approach, respectively, while the impact on axial resolution is negligible. A phantom study shows that compared to digital bandpass filtering, the AFE bandpass filtering enables better use of the dynamic range of the RX electronics, resulting in better generalized contrast-to-noise ratio from 0.44/0.53 to 0.57/0.68 without or with PI.

An integrated front-end vertical hall magnetic sensor fabricated in 0.18 μm low-voltage CMOS technology

An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measurement. To improve the magnetic sensitivity and to obtain low offset, a fully symmetric vertical Hall device (FSVHD) has been optimized with a minimum size design. A new four-phase spinning current modulation associated with a correlated double sampling (CDS) demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage. The vertical Hall sensor chip has been manufactured in a 0.18 μm low-voltage CMOS technology and it occupies an area of 1.54 mm2. The experimental results show in the magnetic field range from –200 to 200 mT, the entire vertical Hall sensor performs with the linearity of 99.9% and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60 μT. Meanwhile, it consumes 4.5 mW at a 3.3 V supply voltage. The proposed vertical Hall sensor is very suitable for the low-cost system-on-chip (SOC) implementation of 2D or 3D magnetic microsystems.

A Dual Frequency Compensation Technique to Improve Stability and Transient Response for a Three Stage Low-Drop-Out Linear Regulator

A novel internal compensation technique named dual frequency compensation is proposed to improve the stability and the transient response of the on-chip output capacitor three stage low-drop-out linear voltage regulator (LDO). It exploits a combination of amplification and differentiation to sufficiently separate the dominant pole from the first non-dominant pole so that the latter is located after the unity gain frequency regardless of the load current value. The proposed LDO regulator is analyzed, designed, and simulated in standard 0.18 µm low voltage CMOS technology. The presented LDO regulator delivers a stable voltage of 1.2 V for an input supply voltage range of 1.35-1.85 V with a maximum line deviation of 4.68mV/V and can supply up to 150mA of the load current. The maximum transient variation of the output voltage is 54.5 mV when the load current pulses from 150mA to 0mA during a fall time of 1µs. The proposed LDO regulator has a low figure of merit compared with recent LDO regulators.

Sensitivity Improvement of a Fully Symmetric Vertical Hall Device Fabricated in 0.18 μm Low-Voltage CMOS Technology

This paper proposes a new implementation method to significantly improve the magnetic sensitivity of a fully symmetric vertical Hall device (FSVHD) based on low-voltage CMOS technology. The FSVHD consists of four identical three-contact vertical Hall elements (3CVHE) and each 3CVHE is located in a low-doped deep n-well. The terminals of the 3CVHE are $\text{n}^{+}$ implanted in an n-well and a $\text{p}^{+}$ implantation in a p-well is performed to act as a trench between two adjacent $\text{n}^{+}$ contacts, enabling Hall current flowing deeply for sensitivity improvement. The influence of the geometry sizes on magnetic sensitivity is exploited utilizing TCAD simulation to obtain the optimized device structure in a $0.18~\mu\text{m}$ CMOS standard technology. The experimental results reveal that the proposed FSVHD with a $\text{p}^{+}$ /p-well trench can attain an improved voltage-related sensitivity of 8.4 mV/VT, which is about 70% higher than that of a conventional FSVHD without a trench in the same CMOS fabrication process, while offset and noise are not degraded. The proposed $\text{p}^{+}$ /p-well implantation trench is a good solution to enhance the sensitivity of a low-voltage CMOS VHD with a low manufacturing cost.

$\pi$ -SCR Device for Broadband ESD Protection in Low-Voltage CMOS Technology

Electrostatic discharge (ESD) protection design is needed for integrated circuits; however, the ESD protection devices near the I/O pad may cause negative impacts on the high-frequency performance. To achieve both excellent ESD robustness and good broadband performance, a silicon-controlled rectifier (SCR) with trigger diodes, a matching inductor, and a reversed diode to form a novel $\pi $ -SCR device is presented in this brief. As compared with the conventional $\pi $ -diode in silicon, the $\pi $ -SCR can reduce the clamping voltage during the critical positive-to- $V_{\text {SS}}$ (PS) ESD test, and the high-frequency performance is not seriously degraded (insertion loss $\pi $ -SCR device does not suffer the latch-up issue in low-voltage CMOS technology, and it has the potential to further reduce the clamping voltage during other ESD tests. Therefore, the novel $\pi $ -SCR device will be a good choice for broadband ESD protection in low-voltage CMOS technology.

Class-AB CMOS output stages suitable for low-voltage amplifiers in nanometer technologies

Inverting and noninverting class-AB output stages suitable for low-voltage nanometer CMOS technologies are presented, analyzed in detail and main design criteria highlighted. The solutions are based on a previous topology that is now modified and improved by avoiding both the use of floating voltage sources and the need for extensive accurate matching. As an example of application, the proposed inverting output stage is exploited in a three-stage amplifier designed in a standard 65-nm CMOS process and supplied from 1 V. Simulations show that the solution provides very good output current drive capability and current efficiency, as it is capable to source/sink a maximum output current of 1.5 mA from a quiescent value of 20 μA. Besides, it allows easy frequency compensation with very good settling performance and linearity.

PETAL: A Multichannel Differential ADC Driver for High-Speed CMOS Image Sensors

Programmable Electronic Termination and Line Driver (PETAL) is a 16-channel ADC driver chip that provides single-ended-to-differential conversion and column biasing for high-speed CMOS image sensors. By increasing the level of integration, the number of driver chips and the associated number of passives and the routing area are reduced, enabling smaller physical cameras. Power dissipation is reduced relative to many commercial approaches by the use of low-voltage CMOS technology and the increased level of integration. The driver chip also supplies programmable bias currents to the sensor, further reducing the number of required components on the camera board. The driver, fabricated in 180-nm CMOS technology, achieves settling to 0.1% in 11 ns with input noise of 89.9- $\mu \text{V}$ rms. The crosstalk between channels is below −56 dB. The power dissipation is 10.5 mW/channel. When applied to the readout of a high-speed X-ray sensor, the prototype reduced board area by 84% (from 100 to 16 mm2) and power dissipation by 25%.

A Reconfigurable Low-Voltage and Low-Power Millimeter-Wave Dual-Band Mixer in 65-nm CMOS

In this paper, we propose, investigate, and demonstrate a reconfigurable low-voltage and low-power millimeter-wave mixer in a 65-nm CMOS, which can be switched as either a subharmonic mixer (SHM) or a fundamental mixer (FM) for the dual-band applications. Based on a modified Gilbert mixer topology, the proposed CMOS mixer can operate at a low supply voltage and low local oscillator (LO) pumping power while providing good performance in both SHM and FM modes. To the best of our knowledge, this is the first reported Gilbert SHM based on the stacked switching quads in a low-voltage CMOS technology. Under 1-V supply voltage and −3-dBm LO pumping power, the measured conversion gain (CG) of the proposed CMOS mixer is −4.8 ± 1.5 dB from 34 to 56 GHz and −0.1 ± 1.5 dB from 17 to 43 GHz in the SHM and FM modes, respectively. The measured double-sideband (DSB) noise figure (NF) is 18.5–20 dB from 37 to 49 GHz and 12.4–14 dB from 17 to 35 GHz in the SHM and FM modes, respectively. The measured input third-order intercept point (IIP3) is 2.9 and 3.4 dBm, respectively, for the SHM and FM modes at the LO frequency of 22 GHz. In addition, the total dc power consumption of the proposed mixer including output buffers is 7 mW in both the operation modes.

TBOR-shaped electro-optic modulator with dual output based on double-layer graphene

We proposed an electro-optic modulator with two-bus one-ring (TBOR) structure to improve the extinction ratio and reduce insert loss. It has a dual output compared with one-bus one-ring structure. In addition, double-layer graphene makes it possible for the modulation in the visible to mid-infrared wavelength range. It shows that this new electro-optic modulator can present two switching states well with low insertion loss, high absorption and high extinction ratio. At λ=1550 nm, when the switching states are based on the chemical potential, μc=0.38 eV and μc=0.4 eV, the insertion losses of both output ports are less than 2 dB, the absorption of the output port coupled via a micro-ring reaches 45 dB and the extinction ratio reaches 14 dB. When the refractive index of the dielectric material is 4.2, the applied voltage will be less than 1.2 V, thus can be used in low-voltage CMOS technology.

A Sizing Methodology for Rise-Time Minimization of Dickson Charge Pumps With Capacitive Loads

A novel sizing methodology for Dickson charge pumps with pure capacitive loads is presented. The methodology is based on dynamic analysis to minimize the rise time of the charge pump up to 25% under a given circuit area. The methodology is validated through the implementation of a six-stage charge pump-based driver in 180-nm standard low-voltage CMOS technology. The driver is used for the excitation of ultrasonic transducers with 34 V at a resonance frequency of 220 KHz. A rise time of only 512 nS is achieved. The driver consumes 10.6 mA drawn from a 5-V supply at a pumping frequency of 50 MHz and occupies an area of 0.2 mm2.

Linearized differential current sensor in low-voltage CMOS

PurposeThis work aims to improve upon the linearity of integrated CMOS current sensors used in switch mode power supply topologies, using a low-cost and low-voltage (less than 1.2 V) CMOS technology node. Improved sensor accuracy contributes to efficiency in switched supplies by reducing measurement errors when it is integrated with closed-loop control.Design/methodology/approachIntegrated current-sensing methods were investigated and CMOS solutions were prioritized. These solutions were implemented and characterized in the desired process and shortcomings were identified. A theoretical analysis accompanied by simulated tests was used to refine improvements which were prototyped. The current sensor prototypes were fabricated and tested.FindingsMeasured and simulated results are presented which show improved linearity in current sensor outputs. Techniques borrowed from analog amplifier design can be used to improve the dynamic range and linearity of current-steered CMOS pairs for measuring current. A current sensor with a gain of 5 V/A operating in a 10 MHz switch mode supply environment is demonstrated.Originality/valueThis paper proposes an alternative approach to creating suitable bias conditions for linearity in a SenseFET topology. The proposed method is compact and architecturally simple in comparison to other techniques.

Design of embedded SCR device to improve ESD robustness of stacked-device output driver in low-voltage CMOS technology

This study proposes a novel design for an embedded silicon-controlled rectifier (SCR) device to improve the electrostatic discharge (ESD) robustness of a stacked-device output driver. A 3×VDD-tolerant stacked-device output driver with embedded SCR is demonstrated using a 0.18μm CMOS process with VDD of 3.3V. This design is verified in a silicon chip, and it is shown that the proposed output driver with embedded SCR can deliver an output voltage of 3×VDD. The ESD robustness can be improved without the use of any additional ESD protection device or layout area. Furthermore, the proposed design can also be used for an n×VDD-tolerant stacked-device output driver to improve its ESD robustness.

High resolution shallow vertical Hall sensor operated with four-phase bi-current spinning current

Vertical Hall-effect devices (VHDs) are CMOS integrated sensors dedicated to the measurement of magnetic field in the plane of the chip. At low frequency, their performances are severely reduced by 1/f noise. This paper presents the capability of a bi-current biasing combined to a four-phase spinning current technique (SCT) to lower 1/f noise and improve the resolution of shallow VHD designed in low-voltage CMOS technologies (LV-VHD). It has been shown that applying the highest achievable biasing current on each phase of the SCT and combining it with a switched gain, the sensor resolution can be optimized. A practical way to implement this technique is proposed, and experiments obtained from a 3μm wide, 25μm long LV-VHD integrated in the AMS 0.35μm CMOS technology show that 1/f noise is efficiently reduced, leading to a resolution of 51μT over a 1.6kHz bandwidth with an average biasing current of only 825μA.

A High-Efficiency Self-Oscillating Class-D Amplifier for Piezoelectric Speakers

The design tradeoffs of the class-D amplifier (CDA) for driving piezoelectric (PZ) speakers are presented, including efficiency, linearity, and electromagnetic interference. An implementation is proposed to achieve high efficiency in the CDA architecture for PZ speakers to extend battery life in mobile devices. A self-oscillating closed-loop architecture is used to obviate the need for a carrier signal generator to achieve low power consumption. The use of stacked-cascode CMOS transistors at the H-bridge output stage provides low-input capacitance to allow high-switching frequency to improve linearity with high efficiency. Moreover, the CDA monolithic implementation achieves 18 $V_{\rm PP}$ output voltage swing in a low-voltage CMOS technology without requiring expensive high-voltage semiconductor devices. The prototype experimental results achieved a minimum THD $+$ N of 0.025%, and a maximum efficiency of 96%. Compared to available CDA for PZ speakers, the proposed CDA achieved higher linearity, lower power consumption, and higher efficiency.

An NTF-enhanced time-based continuous-time sigma-delta modulator

Translation of the amplitude axis to the time axis can be a promising approach to alleviate the analog-to-digital converter's resolution problems in low-voltage CMOS circuits. From this point of view, a noise-coupled time-based continuous-time sigma-delta modulator (TCSDM) based on the asynchronous pulse width modulator (APWM) and the time-to-digital converter (TDC) is presented. Noise-coupling is realized by extracting the time quantization error of the TDC and injecting its delayed version to the input of the APWM. By using a novel implementation of the noise-coupling technique in the proposed TCSDM, the modulator's noise-shaping order is improved by one. Unlike the conventional noise-coupled sigma-delta modulators, in the proposed structure, the need of an extra subtractor at the quantizer input is resolved through merging the excess loop delay compensation path with the proposed noise-coupling branch. Comparative analytical calculations and behavioral simulation results are presented to verify the performance of the proposed time-based modulator. To confirm the validity of the proposed structure, the effects of main circuit non-idealities in the modulator's performance are taken into consideration and the related simulation results are investigated. A digital-friendly implementation of the quantizer in the proposed modulator makes it suitable for low-voltage nanometer CMOS technologies.

Four-phase Bi-current Spinning Current on Shallow Vertical Hall Sensor

Vertical Hall-effect devices (VHDs) are CMOS integrated sensors dedicated to the measurement of magnetic field in the plane of the chip. At low frequency, performances are severely reduced by the 1/f noise. We have recently assessed by FEM simulation the capability of the four-phase spinning current technique (SCT) to lower the 1/f noise on shallow VHD designed in low-voltage CMOS technologies (LV-VHD). It was shown than the highest biasing current could be used on each phase of the SCT, i.e. I13max for phases 1 and 3, and I24max for phases 2 and 4, if the signal on phases 2 and 4 is amplified by a ratio I13max/I24max. Here, we propose a practical way to implement this technique, and for the first time we show experimentally its efficiency to lower the 1/f noise, leading to 51 μT resolution over a 1.6 kHz bandwidth with a average biasing current of only 825 μA.

An improved compact model of the electrical behaviour of the 5-contact vertical Hall-effect device

This paper presents the improvement of an existing design-oriented compact model of the 5-contact vertical Hall-effect sensor integrated in CMOS technology. Such a model should facilitate the work of designers, permitting them to simulate the sensor, the biasing and processing electronics together with the same electrical simulator. Focus is put on the main aspects that alter the electrical response of the sensor: modulation of the conduction channel due to the bias-dependent space charge region thickness, saturation of carrier velocity, asymmetries, and effective channel conduction thickness. The model has been achieved with a subtle mix of theoretical considerations, numerical simulations performed with COMSOL Multiphysics® and experimental data. The parameters extraction procedure is also discussed. The model has been validated on experimental data gathered from two devices, one fabricated in a low-voltage CMOS technology and the other one in a high-voltage CMOS technology. Then, the model is used in order to study offset issues in VHD with external measurement contacts, i.e. VHD integrated in the shallow N-well of low-voltage technologies, and the way the spinning current technique can be used to suppress this offset. A new spinning-current technique is proposed for such a VHD. The simulation results are in perfect accordance with the analytical study. They pave the way for the design of an optimized readout circuitry that may improve the sensor sensitivity while maintaining a very low offset.

A Dual-Junction Single-Photon Avalanche Diode in 130-nm CMOS Technology

A dual-junction single-photon avalanche diode structure is reported in a 130-nm low-voltage CMOS technology. The device comprises two stacked avalanche multiplication regions with virtual guard ring constructions. An 8.6- μm-diameter p-well is placed within a 12.3- μm-diameter deep n-well. At 3-V excess bias, the junctions operate with median dark count rates of 10 and 5 kHz and photon detection efficiencies of 32% at 450 nm and 29% at 670 nm, respectively. We demonstrate that the junction at which a photon is detected can be uniquely distinguished by the dead time of the Geiger mode pulse allowing spectral discrimination by simple digital circuitry.

Graphene–assisted critically–coupled optical ring modulator

Graphene's conductivity at optical frequencies can be varied upon injection of carriers. In the present paper, this effect is used to modulate losses of an optical wave traveling inside a ring cavity. This way an optical modulator based on the critical-coupling concept first introduced by Yariv can be realized. Through numerical simulations, we show that a modulator featuring a bandwidth as large as 100 GHz can be designed with switching energy in the order of few fJ per bit. Also, we show that operations with driving voltages below 1.2 volt could be obtained, thus making the proposed modulator compatible with requirements of low-voltage CMOS technology.

Low Power, High Dynamic Range CMOS Image Sensor Employing Pixel-Level Oversampling <formula formulatype="inline"> <tex Notation="TeX">$\Sigma\Delta$</tex> </formula> Analog-to-Digital Conversion

We present a theoretical analysis, design, and experimental characterization of a CMOS image sensor with pixel-level ΣΔ oversampling analog-to-digital conversion (ADC). The design employs five transistors per-pixel to implement a charge-based ΣΔ ADC at each pixel. In the current design a dynamic regenerative latch comparator is divided into an input transistor, which is contained within each pixel, and the remaining comparator structure shared among the pixels of each column. A charge feedback digital-to-analog converter (DAC) is implemented at each pixel with a three-transistor structure. As opposed to more traditional CMOS image sensors, this image sensor architecture is suitable for implementations in advanced low supply voltage CMOS technologies since its dynamic range is not affected by the reduction of the pixel reset voltage. In addition, similar to the readout methods in low power random access memory designs, this pixel readout architecture does not employ any active amplifiers which allows for low static power operation. Experimental characterization of a prototype fabricated in a 0.35 μm silicided CMOS technology is presented. The estimated power consumption of the fully integrated 128 × 128 imager including decimation filters and I/O interface is 60 nW/pixel at 30 frames per second for 8-bits per-pixel. A peak signal-to-noise ratio of 52 dB and intra-scene dynamic range of 74 dB were measured. The dynamic range was extended to 91 dB through control of the in-pixel DAC supply voltage over the range of 0.8 V-3.3 V.