Four-phase Bi-current Spinning Current on Shallow Vertical Hall Sensor

Abstract

Vertical Hall-effect devices (VHDs) are CMOS integrated sensors dedicated to the measurement of magnetic field in the plane of the chip. At low frequency, performances are severely reduced by the 1/f noise. We have recently assessed by FEM simulation the capability of the four-phase spinning current technique (SCT) to lower the 1/f noise on shallow VHD designed in low-voltage CMOS technologies (LV-VHD). It was shown than the highest biasing current could be used on each phase of the SCT, i.e. I13max for phases 1 and 3, and I24max for phases 2 and 4, if the signal on phases 2 and 4 is amplified by a ratio I13max/I24max. Here, we propose a practical way to implement this technique, and for the first time we show experimentally its efficiency to lower the 1/f noise, leading to 51 μT resolution over a 1.6 kHz bandwidth with a average biasing current of only 825 μA.