Low-voltage CMOS Current-mode Research Articles

High-PSRR, Low-Voltage CMOS Current Mode Reference Circuit Using Self-Regulator with Adaptive Biasing Technique

High-PSRR, Low-Voltage CMOS Current Mode Reference Circuit Using Self-Regulator with Adaptive Biasing Technique

Low-voltage subthreshold CMOS current mode circuits: Design and applications

The world has migrated to portable applications ranging from smart phones to Lab on a Chip applications. However they come with a new set of challenges for analog IC designers. Low voltage operation, small area and low noise are the critical design criteria for portable devices. This paper presents a gm/ID based design methodology for low voltage current mode circuits using standard CMOS technology. A second generation current conveyor (CCII) and a current feedback operational amplifier (CFA) are designed using the discussed design procedure. Both circuits operate from a single 0.4V supply. The CCII is used to implement an instrumentation amplifier. Multiple applications are implemented using the CFA. Post layout simulation using TSMC 90nm and UMC 130nm technology show that the presented design procedure is an attractive solution for low voltage CMOS current mode circuits.

An improved high speed, and low voltage CMOS current mode logic latch

A high-speed, low voltage CMOS current mode logic (CML) latch, that has high input, and output voltage dynamic ranges, is proposed in this paper. The input common-mode voltage, and the output voltage dynamic range behavior are analyzed for the proposed latch and the most common (or typical) latch. Both CML latch structures were designed in a 0.18 $$\upmu$$μm RFCMOS technology with a nominal voltage $$V_{DD}=1.8$$VDD=1.8 V. The output voltage errors, which the main cause is due to input voltage variations, even when the circuit is in latch mode, are analyzed in this paper. The post-layout results, using a clock frequency at 10 GHz, and the same bias current of 6 mA for both circuits shows an increment of 60 % for the output voltage swing in the proposed latch versus the typical latch. Besides, this topology being more robust it can be used for higher frequencies up to 20 GHz.

Low-Voltage Current-Mode WTA/LTA Circuit

A low-voltage CMOS current-mode Winner take all and looser take all circuits are designed in 0.35 µm standard CMOS technology.Simulation results using HSPICE that verify the functionality of circuit with 1.5 V supply are presented. The circuit can find application in the implementation of Fuzzy and Neural Network circuits.

A Low-Voltage CMOS Current Mode Integrated Transmitter Front-end for 2.4-GHz Wireless Communications

This paper presents a low-voltage low-power current mode transmitter front-end for 2.4 GHz wireless communication applications, which is fabricated in a chartered 0.18-mm CMOS technology. The direct up-conversion is implemented with a current mode mixer employing a novel input driver stage, which can significantly improve the linearity and consume a small amount of DC current. The driver amplifier utilizes a transimpedance amplifier as the first stage and employs an inter-stage capacitive cross-coupling technique which enhances the power conversion gain as well as high linearity. The measured results show that at 2.4GHz, the transmitter front-end provides 15.5dB of power conversion gain, output P-1dB of 3dBm, and the output-referred third-order intercept point (OIP3) of 13.8dBm, while drawing only 6 mA from the transmitter front-end under a supply voltage of 1.2 V. The chip area including testing pads is only 0.9 mm 1.1 mm. Index Terms –CMOS, up-conversion mixer, driver amplifier, transmitter, current mode, high linearity, low-power

Low-voltage CMOS current-mode circuits: topology and characteristics

The author presents an in-depth study of the topologies and characteristics of low-voltage CMOS current amplifiers. The input impedance, output impedance, bandwidth, noise performance, and dynamic range of current amplifiers are investigated both analytically and numerically. Several new circuit techniques specific to low-voltage CMOS current-mode circuits including pseudo-cascode, current–current feedback, inductive series peaking, and joint resistive/inductive series peaking and current–current feedback for bandwidth enhancement, output impedance boosting, and dynamic range improvement are proposed. To provide a quantitative comparison and to quantify the effect of these new circuit techniques, the current amplifiers investigated are implemented in TSMC 0.18 μm 1.8 V CMOS technology and analysed using Spectre from Cadence Design Systems with BSIM3V3 device models that count for both device parasitics and high-order effects. Simulation results are compared with those from analytical analysis.

Low-voltage CMOS current-mode preamplifier: analysis and design

This paper presents the analysis and design of a new low-voltage fully balanced differential CMOS current-mode preamplifier for multi-Gbps series data communications. The minimum supply voltage of the proposed preamplifier is V/sub T/+V/sub sat/. The preamplifier employs a balanced configuration to achieve large bandwidth and to minimize the effect of bias-dependent mismatches. Two new bandwidth enhancement techniques, namely inductive series peaking and current feedback that are specific to low-voltage CMOS current-mode circuits, are introduced. The inductive series peaking technique utilizes the resonant characteristics of LC networks to achieve both a flat frequency response and maximum bandwidth. Current feedback extends bandwidth, lowers input impedance, and improves dynamic range. The employment of both techniques further increases the bandwidth, reduces the value of the series peaking inductor, and improves noise performance of the pre-amplifier at high frequencies. The preamplifier has been designed using a 0.18-/spl mu/m 6-metal 1-poly 1.8-V CMOS technology. Simulation results from Spectre with BSIM3.3 device models that account for device parasitics demonstrate that the preamplifier has a flat frequency response with 25.3 dB dc current gain or equivalently 60 dB/spl Omega/ transimpedance gain with a 50-/spl Omega/ load and bandwidth of 2.15 GHz.

A New Inductor Series-Peaking Technique for Bandwidth Enhancement of CMOS Current-Mode Circuits

This paper introduces a new inductor series-peaking technique for bandwidth enhancement of low-voltage CMOS current-mode circuits. The peaking inductor is in series with the capacitor constituting the dominant pole. It boosts the bandwidth by utilizing the resonance characteristics of LC networks. To reduce the value of the peaking inductor, a new negative current-current feedback mechanism is proposed. The employment of both inductive peaking and current feedback further increases the bandwidth. Both the inductor series-peaking and the current-current feedback do not affect the supply voltage and DC biasing conditions. Theoretical analysis and simulation results show that a significant bandwidth enhancement is achieved.