Low Time Overhead Research Articles

Assessing LES models based on tabulated chemistry for the simulation of Diesel spray combustion

In the context of large-eddy simulation (LES) of Diesel engine combustion, two LES combustion models are proposed. Their ability to predict autoignition delays and heat release of an autoigniting liquid α-methylnaphthalene/n-decane jet injected into a constant-volume chamber under Diesel-like conditions is assessed. These models retain the tabulation of a complex chemistry scheme using autoigniting homogeneous reactors (HR) at constant pressure. This allows accounting for the chemical complexity of heavy hydrocarbon fuels over the wide range of conditions representative for Diesel engines, at comparatively low CPU time overhead. The tabulated homogeneous reactor (THR) approach assumes the local structure of the reaction zone to be that of an HR, while the approximated diffusion flame (ADF) approach is based on autoigniting strained diffusion flames. Two variants of each approach are considered, either neglecting sub-grid-scale mixture fraction variance (THR and ADF models), or accounting for it via a presumed β-PDF (THR-pdf and ADF–PCM models). LES results indicate that the ADF model assuming diffusion flame structures tends to predict faster propagation of the combustion toward less reactive mixture fractions then the THR model. Moreover, neglecting the mixture fraction fluctuations strongly overestimates initial experimental heat release rates after autoignition. Comparison between models shows that this assumption yields higher reaction rates and temperature levels close to the stoichiometric mixture fraction zones. Predictions in terms of autoignition are remarkably close with all models, and exhibit very few variations from one realization to the other. Variations in global heat release rate become more apparent for different realizations at later instants, in relation to the interaction of large flow scales with combustion.

Steal Tree

Work stealing is a popular approach to scheduling task-parallel programs. The flexibility inherent in work stealing when dealing with load imbalance results in seemingly irregular computation structures, complicating the study of its runtime behavior. In this paper, we present an approach to efficiently trace async-finish parallel programs scheduled using work stealing. We identify key properties that allow us to trace the execution of tasks with low time and space overheads. We also study the usefulness of the proposed schemes in supporting algorithms for data-race detection and retentive stealing presented in the literature. We demonstrate that the perturbation due to tracing is within the variation in the execution time with 99% confidence and the traces are concise, amounting to a few tens of kilobytes per thread in most cases. We also demonstrate that the traces enable significant reductions in the cost of detecting data races and result in low, stable space overheads in supporting retentive stealing for async-finish programs.

Graph-tree-based software control flow checking for COTS processors on pico-satellites

This paper proposes a generic high-performance and low-time-overhead software control flow checking solution, graph-tree-based control flow checking (GTCFC) for space-borne commercial-off-the-shelf (COTS) processors. A graph tree data structure with a topology similar to common trees is introduced to transform the control flow graphs of target programs. This together with design of IDs and signatures of its vertices and edges allows for an easy check of legality of actual branching during target program execution. As a result, the algorithm not only is capable of detecting all single and multiple branching errors with low latency and time overheads along with a linear-complexity space overhead, but also remains generic among arbitrary instruction sets and independent of any specific hardware. Tests of the algorithm using a COTS-processor-based on-board computer (OBC) of in-service ZDPS-1A pico-satellite products show that GTCFC can detect over 90% of the randomly injected and all-pattern-covering branching errors for different types of target programs, with performance and overheads consistent with the theoretical analysis; and beats well-established preeminent control flow checking algorithms in these dimensions. Furthermore, it is validated that GTCGC not only can be accommodated in pico-satellites conveniently with still sufficient system margins left, but also has the ability to minimize the risk of control flow errors being undetected in their space missions. Therefore, due to its effectiveness, efficiency, and compatibility, the GTCFC solution is ready for applications on COTS processors on pico-satellites in their real space missions.

An Exchange Framework for Intrusion Alarm Reduction in Mobile Ad-hoc Networks

Numerous Intrusion Detection Systems (IDSs) have been developed for MANETs; however, comparatively little research focuses on intrusion alarm exchange and validation in Mobile Ad Hoc Networks (MANETs). We provide a secure alarm exchange framework for proactive MANET routing protocols and use Optimized Link State Routing model (OLSR) for the implementation. In our solution, alarms can be aggregated at a group coordinator for advanced alarm verification and reduction. This model can solve two major challenges in MANETs: lack of a centralized authority and dynamic topology caused by mobility. Furthermore, it also provides the foundations for local and global alarm validations. Unnecessary responses to false or forged alarms can be prevented if intrusion alarms are proved to be authentic and accurate. Our model selects the node with the best connectivity as the temporary centralized node for collecting all local alarms. Subsequently, it utilizes majority-voting strategy to detect false alarms. After false alarm reduction, an accurate local alarm is broadcast as a global alarm for notifying the entire network of the attacker existence. This model has the advantages of alarm reduction and low time overhead. The experimental results demonstrate that our solution is scalable and is not influenced by mobility. Extra alarm exchange and verification messages cause low time and message overhead.

Photonic Interconnection Network Architectures Using Wavelength-Selective Spatial Routing for Chip-Scale Communications

The overall performance of modern computing systems is increasingly determined by the characteristics of the interconnection network used to provide communication links between on-chip cores and off-chip memory. Photonic technology has been proposed as an alternative to traditional electronic interconnects because of its advantages in bandwidth density, latency, and power efficiency. Circuit-switched photonic interconnect topologies take advantage of the optical spectrum to create high-bandwidth transmission links through the transmission of data channels on multiple parallel wavelengths; however, this technique suffers from low path diversity and high setup time overhead, which induces high network resource contention, unfairness, and long latencies. This work improves upon the circuit-switching paradigm by introducing the use of on-chip wavelength-selective spatial routing to produce multiple logical communication layers on a single physical plane. This technique yields higher path diversity in photonic interconnection networks, demonstrating as much as 764% saturation bandwidth improvement with synthetic traffic and as much as 89% improvement in execution time and energy dissipation for traffic from scientific application traces.

Abnormal Access Request Detection based Secure Storage Area Network System

In order to ensure security of the enormous data stored in the storage area network system, current secure technology need large time and space consumption and extra storage space. The artificial immune algorithm can efficiently detect abnormal data. In order to keep high I/O performance of storage area network system, we use the artificial immune algorithm to detect the abnormal access request of the storage area network system, and we implement the secure storage area network system named ADSSAN. We present the structure of the metadata server with the central abnormal access request detection module, the storage device with the associate abnormal access request detection module and the secure storage area network system. The definitions of main elements are given. By analyzing the feature of the storage area network system, the master-slave artificial immune algorithm is presented. The central abnormal access request detection module generates all detectors and distributes part of detectors to the associate abnormal access request detection module in the storage servers. Then the distributed strategy of artificial immune algorithm can be used to reduce the time and space consumption of generating detectors and improve performance of abnormal access request detection. The prototype of abnormal access request detection module is implemented and tested, the result shows that the master-slave artificial immune algorithm can accurately detect abnormal access request with low time and space overhead. At last, the prototype of secure storage area network system is implemented on Lustre and evaluated its I/O performance. The result shows that the central and associate abnormal access request detection module can efficiently check out abnormal access request, and the prototype of secure storage area network system can keep high I/O performance.

A Software Behavior Automaton Model Based on System Call and Context

According to the problems of high time overhead of capturing the system call context by walking the stack and inaccuracy of system call argument policies for traditional software behavior models, a software behavior automaton model based on system call and context is proposed. First, data flow information containing system call argument policies is combined with software control flow and is used to anomaly detection of software behavior. Second, a new approach of context value for capturing system call context with accuracy and low time overhead is proposed. Third, system call argument context based on system call context is introduced and system call argument policies based on context including system call context and system call argument context are presented. The experimental results show that the software behavior automaton model based on system call and context can capture the system call context accurately with low time overhead, can describe system call argument policies precisely, and can well detect the anomaly of software behavior based on control flow and data flow.

A method to improve interrupt latency in real-time OS kernels

Interrupt latency has great impact on the real time and predictability of real-time operating system kernels. In traditional implementation of real-time kernels, interrupts are frequently disabled in system service routines, critical sections, etc., which causes kernel interrupt latency. In this paper we propose a method called PIL (Predictive Interrupt Latency). PIL reduces interrupt latency by never disabling interrupts during any system service routines. Moreover, it makes interrupt latency vary little, which improves the predictability in the response time for external events. We have implemented the PIL method in an OSEK-compatible operating system - SmartOSEK OS. Experimental results show PIL improves real time and predictability of real-time systems with low time and space overheads.

High Repair Efficiency BIRA Algorithm with a Line Fault Scheme

With the rapid increase occurring in both the capacity and density of memory products, test and repair issues have become highly challenging. Memory repair is an effective and essential methodology for improving memory yield. An SoC utilizes builtin redundancy analysis (BIRA) with built-in self-test for improving memory yield and reliability. This letter proposes a new heuristic algorithm and new hardware architecture for the BIRA scheme. Experimental results indicate that the proposed algorithm shows near-optimal repair efficiency in combination with low area and time overheads.

Low-Power Soft Error Hardened Latch

This paper presents a low-power soft error-hardened latch suitable for reliable circuit operation. The proposed circuit uses redundant feedback loop to protect latch against soft error on the internal nodes, and transmission gate and Schmitt-trigger circuit to filter out transient resulting from particle hit on combinational logic. The proposed circuit has low power consumption with negative setup time and low timing overhead. The HSPICE post-layout simulation in 90nm CMOS technology reveals that circuit is able to recover from almost any single particle strike on internal nodes and tolerates input SETs up to 130ps of duration.

Static Analysis Based Correctness Verification for Mandatory Access Control Framework

Current researches on correctness verification for the mandatory access control framework of operating systems mainly focus on authorization hooks placement verification.Based on TrustedBSD MAC framework,this paper analyses the correctness verification problem for mandatory access control framework,and proposes complete initialization and complete destruction for security labels,as well as complete authorization for access.In order to enforce these verifications,this paper also presents a path-sensitive and user-defined-rule based static analysis approach.This approach verifies the accuracy and completeness of hooks placement of the mandatory access control framework through extending the compiler integrated static analysis tool-mygcc.It achieves high path cover,low false positive rate and time overhead.

Fair Watermarking Using Combinatorial Isolation Lemmas

Watermarking is one of the most effective mechanisms for intellectual property protection (IPP) of hardware and software artifacts. Numerous watermarking-based IPP techniques have been proposed that satisfy a spectrum of IPP desiderata, including full preservation of functionality, low timing, area and power overhead, transparency to the synthesis and compilation process, and resilience against attacks. Two objectives that are very important, but, until now have not yet been properly addressed, are credibility and fairness. We present a new watermarking technique that specifically targets credibility and fairness. Using a combinatorial result by Valiant and Vazirani, we demonstrate how these two desiderata can be achieved during the watermarking of a satisfiability (SAT) instance. The effectiveness of the technique is demonstrated on both specially created examples, where the number of solutions is known, as well as on common computer-aided design and operational research SAT benchmark instances.

Assembly instruction level reverse execution for debugging

Assembly instruction level reverse execution provides a programmer with the ability to return a program to a previous state in its execution history via execution of a "reverse program." The ability to execute a program in reverse is advantageous for shortening software development time. Conventional techniques for recovering a state rely on saving the state into a record before the state is destroyed. However, state-saving causes significant memory and time overheads during forward execution.The proposed method introduces a reverse execution methodology at the assembly instruction level with low memory and time overheads. The methodology generates, from a program, a reverse program by which a destroyed state is almost always regenerated rather than being restored from a record. This significantly reduces state-saving.The methodology has been implemented on a PowerPC processor with a custom made debugger. As compared to previous work, all of which heavily use state-saving techniques, the experimental results show from 2X to 2206X reduction in run-time memory usage, from 1.5X to 403X reduction in forward execution time overhead and from 1.2X to 2.32X reduction in forward execution time for the tested benchmarks. Furthermore, due to the reduction in memory usage, our method can provide reverse execution in many cases where other methods run out of available memory. However, for cases where there is enough memory available, our method results in 1.16X to 1.89X slow down in reverse execution.

Efficient Execution of Pure Object-Oriented Programs by Follow-up Compilation

Dynamic type checking and method binding slows pure object-oriented programs such as those written in Smalltalk. Dynamic method lookup is needed to support method overriding and type-method conformance. We have developed a platform independent technique that implements method overriding efficiently for pure object-oriented languages. The technique involves binding non-overridden method calls at compile time. The overridden method calls are also resolved (and bound) statically using simple inferences. Overridden method bindings are corrected dynamically using an Overridden Method Dictionary. Using simulations, we demonstrate that this technique offers 35%-70% reduction in the average method lookup delay over the Berkeley Smalltalk implementation. This technique has very low compile time overhead, memory overhead, does not need specialized hardware and allows shared code pages in concurrent programs. For programs which may be re-used, it is proper to have a follow-up compilation to generate efficient code after the program development is complete.

Probability graph based data hoarding for mobile environment

The vision of mobile environment is severely challenged by disconnected operation. Automated hoarding is an attractive approach solution to this issue. On the other hand, the large overhead of automatic hoarding algorithm is a serious problem for handheld devices. In this paper, we propose an application-independent automatic hoarding algorithm based on probability graph. Simulation results show that it can improve cache hit rate with low time and space overhead in disconnected operation effectively, especially for small cache size, which makes our proposed algorithm preferable for handheld devices.

Instruction-level reverse execution for debugging

The ability to execute a program in reverse is advantageous for shortening debug time. This paper presents a reverse execution methodology at the assembly instruction-level with low memory and time overheads. The core idea of this approach is to generate a reverse program able to undo, in almost all cases, normal forward execution of an assembly instruction in the program being debugged. The methodology has been implemented on a PowerPC processor in a custom made debugger. Compared to previous work -- all of which use a variety of state saving techniques -- the experimental results show 2.5X to 400X memory overhead reduction for the tested benchmarks. Furthermore, the results with the same benchmarks show an average of 4.1X to 5.7X time overhead reduction.

Space compression revisited

This paper discusses new space compression techniques for built-in self-testing (BIST) of VLSI circuits based on the use of compact test sets to minimize the storage requirements for the circuit under test (CUT) while maintaining the fault coverage information. The techniques utilize the concepts of Hamming distance and sequence weights along with failure probabilities of errors in the selection of specific gates for merger of pairs of output streams from the CUT. The outputs coming out of the space compressor may eventually be fed into a time compressor to derive the signature for the circuit. The concept is extended to establish generalized mergeability criteria for merging an arbitrary number of output bit streams under conditions of both stochastic independence and dependence of line errors. The proposed techniques guarantee rather simple design with high fault coverage for single stuck-line faults, with low CPU simulation time and acceptable area overhead. Design algorithms are also proposed, and the simplicity and ease of implementation are demonstrated with examples, primarily through extensive simulation runs on ISCAS 85 combinational benchmark circuits with FSIM, ATALANTA, and COMPACTEST. The paper also provides performance comparisons of the designed space compressors with the conventional linear parity tree space compressor.

Integrating Image Computation in Undergraduate Level Data-Structure Education

There is a growing need for expertise both in image analysis and in software engineering. To date, these two areas have been taught separately in an undergraduate computer and information science curriculum. However, we have found that introduction to image analysis can be easily integrated in data-structure courses without detracting from the original goal of teaching data structures. Some of the image processing tasks offer a natural way to introduce basic data structures such as arrays, queues, stacks, trees and hash tables. Not only does this integrated strategy expose the students to image related manipulations at an early stage of the curriculum but it also imparts cohesiveness to the data-structure assignments and brings them closer to real life. In this paper we present a set of programming assignments that integrates undergraduate data-structure education with image processing tasks. These assignments can be incorporated in existing data-structure courses with low time and software overheads. We have used these assignment sets thrice: once in a 10-week duration data-structure course at the University of California, Santa Barbara and the other two times in 15-week duration courses at the University of South Florida, Tampa.

Low overhead fault-tolerant FPGA systems

Fault-tolerance is an important system metric for many operating environments, from automotive to space exploration. The conventional technique for improving system reliability is through component replication, which usually comes at significant cost: increased design time, testing, power consumption, volume, and weight. We have developed a new fault-tolerance approach that capitalizes on the unique reconfiguration capabilities of field programmable gate arrays (FPGA's). The physical design is partitioned into a set of tiles. In response to a component failure, a functionally equivalent tile that does not rely on the faulty component replaces the affected tile. Unlike application specific integrated circuit (ASIC) and microprocessor design methods, which result in fixed structures, this technique allows a single physical component to provide redundant backup for several types of components. Experimental results conducted on a subset of the MCNC benchmarks demonstrate a high level of reliability with low timing and hardware overhead.

Job scheduling in mesh multicomputers

A new approach for dynamic job scheduling in mesh-connected multiprocessor systems, which supports a multiuser environment, is proposed in this paper. Our approach combines a submesh reservation policy with a priority-based scheduling policy to obtain high performance in terms of high throughput, high utilization, and low turn-around times for jobs. This high performance is achieved at the expense of scheduling jobs in a strictly fair, FCFS fashion; in fact, the algorithm is parameterized to allow trade-offs between performance and (short-term) POPS fairness. The proposed scheduler can be used with any submesh allocation policy. A fast and efficient implementation of the proposed scheduler has also been presented. The performance of the proposed scheme has been compared with the FCFS policy, the only existing scheduling strategy for meshes, to demonstrate the effectiveness of the proposed approach. Simulation results indicate that our scheduling strategy outperforms the FCFS policy significantly. Specifically, our strategy significantly reduces the average waiting delay of jobs over the FCFS policy. The fast implementation of the proposed scheduler results in low allocation and deallocation time overhead, as well as low space overhead.