Low-temperature Polycrystalline Si Research Articles

Homojunction structure amorphous oxide thin film transistors with ultra-high mobility

Amorphous oxide semiconductors (AOS) have unique advantages in transparent and flexible thin film transistors (TFTs) applications, compared to low-temperature polycrystalline-Si (LTPS). However, intrinsic AOS TFTs are difficult to obtain field-effect mobility (μ FE) higher than LTPS (100 cm2/(V·s)). Here, we design ZnAlSnO (ZATO) homojunction structure TFTs to obtain μ FE = 113.8 cm2/(V·s). The device demonstrates optimized comprehensive electrical properties with an off-current of about 1.5 × 10–11 A, a threshold voltage of –1.71 V, and a subthreshold swing of 0.372 V/dec. There are two kinds of gradient coupled in the homojunction active layer, which are micro-crystallization and carrier suppressor concentration gradient distribution so that the device can reduce off-current and shift the threshold voltage positively while maintaining high field-effect mobility. Our research in the homojunction active layer points to a promising direction for obtaining excellent-performance AOS TFTs.

Mobility improvement of LTPS thin film transistor using stacked capping layer

Low-temperature polycrystalline Si (LTPS) has been widely used to achieve large-area and high-speed TFT devices. In this regard, the enhancement in the mobility and stability of LTPS TFTs was investigated with the insertion of amorphous silicon (a-Si:H) capping layers at the insulator/poly-Si junction. Prior to capping layer deposition, the polycrystalline Si active region was plasma pre-treated under N2O or NH3/N2O ambience to refine the device characteristics. A high field effect mobility (μFE) of 90 cm2/Vs with a subthreshold swing (SS) of 1.21 V/dec was obtained from N2O treated non-capped LTPS TFT. The inclusion of a-Si:H(n)/a-Si:H(i) stacked capping layer at the gate insulator/poly-Si junction enhanced μFE to 152 cm2/Vs and decreased the SS to 0.69 V/dec. In contrast, the single capping layer of a-Si:H(i) and a-Si:H(n) showed feeble μFE improvements. The mechanism behind the μFE increase for the a-Si:H(n)/a-Si:H(i) stacked capping layer was explained using the atlas TCAD simulator. The grain boundary trap (Ntrap) density also decreased drastically with the insertion of the capping layer. A low and stable Ntrap value of 3.8 × 1011 cm−3 was obtained for a-Si:H(n)/a-Si:H(i) stacked capping layer with N2O pre-treatment, which may play a major role in enhancing the mobility and can be implemented for next-generation LTPS TFTs.

Origin of Spontaneous Degradation of Flexible Poly-Si TFTs After Dynamic Bending

The origin of an abnormal spontaneous degradation of low-temperature polycrystalline Si (LTPS) thin-film transistors (TFTs) is investigated. After being subjected to dynamic bending stress, LTPS TFTs will continuously degrade when stored in a normal condition. Studies have shown that the interaction between the sensitive area of the TFTs and the O2 in ambient environment causes the spontaneous degradation. Defects at the gate oxide/channel interface generated by mechanical stress continuously capturing electrons with the help of oxygen is regarded as the origin of spontaneous degradation. In contrast, moisture in air can effectively suppress spontaneous degradation by reacting with the above defects to form relatively stable atom groups.

Inhibiting the Kink Effect and Hot-Carrier Stress Degradation Using Dual-Gate Low-Temperature Poly-Si TFTs

This study examines the appearance of a kink effect phenomenon in the I $_{\mathbf {D}}$ -V $_{\mathbf {D}}$ electrical characteristics of low-temperature polycrystalline Si thin-film transistors (LTPS TFTs) after high-current-induced hot-carrier stress (HCS). During HCS, electron–hole pairs were generated in the channel near the drain terminal owing to impact ionization. Next, the electrons were repelled towar the source by the drain electric field, thereby inducing the floating body effect, which lowered the source barrier. In addition, a dual-gate-structured LTPS was found to inhibit the electrical degradation caused by HCS. The COMSOL simulation indicated that in the dual-gate structure, holes at the upper and lower margins of the channel were inverted and inhibited the degradation caused by the floating body effect. Therefore, the use of dual-gate LTPS TFTs could facilitate high-current gate-on-array circuit applications in display panels.

Spontaneous Degradation of Flexible Poly-Si TFTs Subject to Dynamic Bending Stress

An abnormal spontaneous degradation of polycrystalline Si thin-film transistors (TFTs) subject to dynamic bending stress is reported. Dynamic mechanical bending along either the channel-width or length direction causes degradation in flexible low-temperature polycrystalline Si TFTs, such as on-state current increase and threshold voltage positive shift. However, after the mechanical stress is removed, TFTs stored in a normal ambient continue to degrade spontaneously, with similar degradation behaviors. The amount of spontaneous degradation can be larger than the mechanical bending-induced degradation and is the most significant for a moderate number of bending cycles. The spontaneous degradation is a new challenge to TFT reliability under mechanical stress.

Review—Technology Trends of Poly-Si TFTs from the Viewpoints of Crystallization and Device Performance

Thin-film transistors (TFTs) utilizing low-temperature polycrystalline-Si (LTPS) are critical for system-on-panel applications. The requirements for LTPS are a high quality, a large grain size and position control of the nucleation. Many promising crystallization methods have been developed to satisfy these requirements. Herein, two scientific discoveries related to the low-temperature crystallization and high-performance TFT structure using the tunnel effect are introduced. Hydrogens in an amorphous (a-Si) film greatly accelerate the crystal velocity and improved the crystallinity of the excimer-laser annealing (ELA) poly-Si film, thereby providing a high-quality, a large-grained film referred to as secondary-grain film, under the solid-phase condition. In addition, a soft X-ray crystallization (SXC) method was developed. It reduces the threshold temperature of crystallization for a-Si, SiXGe1-X and Ge films by 100°C–140°C in comparison to that for films prepared by conventional thermal crystallization. The SXC method is expected to become the critical low-temperature crystallization method in the era of the flexible electronics. On the other hand, although high-performance TFTs that utilize large single-crystalline grains have been intensively researched, such research has not been successful from the viewpoint of mass production. A novel device structure – tunneling dielectric TFT (TDTFT)–has been developed. The TDTFT reduces the gate-off current to less than 1/10 of that with a conventional TFT. In addition, the TDTFT improved the hump effect. We conclude that the triple-gate (Fin) TDTFT will be a promising candidate for next-generation poly-Si TFT structures.

(Invited) Technology Trend of Poly-Si TFT from Viewpoints of Crystallization and Device Performance

TFTs utilizing the Low-Temperature Polycrystalline-Si (LTPS) are very crucial for the system-on-glass. The requirements for the LTPS are a high quality, a large grain size and a position control of the nucleation. To satisfy those requirements, the promising crystallization methods have been presented. In addition, the device structures such as the double gate TFT and the tunnel type TFT have been developed. The excimer laser annealing provided a large grained film with a high-quality. It was also clarified that hydrogens in a-Si film greatly accelerated the crystal velocity and improved the crystallinity of the poly-Si film. A soft X-ray crystallization (SXC) reduced the threshold temperature of crystallization for a-Si, Ge and SixGe1-x films by 100-150 oC as compared with the thermal crystallization. Although the high-performance TFT utilizing the large single crystalline grains has been intensively researched, it does not successfully operate from the productive viewpoint. Tunneling Dielectric Thin-Film Transistor (TDTFT) was proposed and fabricated. It reduced the gate-off current less than 1/10 in comparison with a conv. TFT. In addition, the TDTFT improved the hump effect. We conclude that TDTFT will be suitable as a promising candidate of the next generation poly-Si TFT structure.

(Invited) Technology Trend of Poly-Si TFT from Viewpoints of Crystallization and Device Performance

Thin-film transistors (TFTs) utilizing the Low-Temperature Polycrystalline-Si (LTPS) as their active areas are very crucial for the system-on-glass (SOG). The liquid-crystal display (LCD) or organic light emitting diode display are fabricated in the display area and their controls are performed by the micro-computer that is formed in the peripheral area. The application of high-performance poly-Si TFTs to the high-definition LCD light valves for projectors was reported for the first time[1]. Therefore, the requirements for the recrystallized Si film are a high quality, a large grain formation and a position control of the nucleation. To satisfy those requirements, a super lateral growth (SLG)[2] using the excimer laser annealing (ELA), a phase-modulated ELA[3], a solid-phase crystallization followed by ELA[1], a low-temperature solid-phase excimer laser crystallization[4], a Pd:YAG laser crystallization[5], a soft X-ray crystallization (SXC)[6] have been studied. For the device structure, the double gate TFT[7] and the tunnel TFT[8] have been developed. In our group, the low-temperature crystallization methods and the novel TFT utilizing tunnel effect have been researched. Low-temperature crystallization: For the ELA method, the mechanism of multi-pulse ELA crystallization has been clarified and a large grained film with a high-quality[4] was provided. In addition, hydrogens in a-Si film greatly influenced the crystallinity and grain size of the poly-Si[9,10] and we discovered the advantage in ELA of hydrogen–modulation-doped a-Silicon Layer[11]. For the SXC, a low-temperature crystallization of a-Si, Ge and SixGe1-x film was researched and developed using the short undulator as a light source. The fundamental process of the SXC-method is a local excitation of core electrons to vacuum level by photons followed by the atom movement due to the Coulomb repulsion, which results in the lower temperature process. The SXC-method reduced the threshold temperature of crystallization for a-Si, Ge and SixGe1-x film by 100 - 150 degree C as compared with the conv. thermal crystallization. Novel TFT: Although the high-performance TFT with the high carrier mobility and low leakage current utilizing the large single crystalline grains has been intensively researched, it does not successfully operates from the productive viewpoint[12]. Tunneling Dielectric Thin-Film Transistor (TDTFT) was proposed and fabricated in a bottom-gate structure. Using a 1.7-nm-thick SiNx film, it reduced the gate-off current less than 1/10 in comparison with a conv. TFT. In addition, the TDTFT improved the hump effect as shown in Fig.1[13]. It is considered that the fixed charge in the SiNx film suppresses the formation of the parasitic channel in the poly-Si edge by the Coulomb repulsion. We conclude that TDTFT will suitable as a candidate of the next generation TFT structure.

Effect of flash lamp annealing on electrical activation in boron-implanted polycrystalline Si thin films

Boron-implanted polycrystalline Si thin films on glass substrates were subjected to a short duration (1ms) of intense visible light irradiation generated via a high-powered Xe arc lamp. The disordered Si atomic structure absorbs the intense visible light resulting from flash lamp annealing. The subsequent rapid heating results in the electrical activation of boron-implanted Si thin films, which is empirically observed using Hall measurements. The electrical activation is verified by the observed increase in the crystalline component of the Si structures resulting in higher transmittance. The feasibility of flash lamp annealing has also been demonstrated via a theoretical thermal prediction, indicating that the flash lamp annealing is applicable to low-temperature polycrystalline Si thin films.

High performance low temperature polycrystalline Si thin-film transistors fabricated by silicide seed-induced lateral crystallization

A novel and simple crystallization method for high performance polycrystalline silicon (poly-Si) thin-film transistors (TFTs) using Ni silicide seed-induced lateral crystallization (SILC) was proposed in this study, and it includes no additional deposition and/or etching processes that are not found in the fabrication of conventional metal-induced lateral crystallization (MILC) TFTs. The poly-Si thin films crystallized by SILC were characterized by x-ray photoelectron spectroscopy (XPS), x-ray diffraction (XRD), field emission scanning electron microscopy (FESEM), and Micro-Raman spectroscopy. The electrical properties were obtained from ID-VG transfer curves and the interface trap density was determined by Levinson plot analysis. The results show that SILC poly-Si films have lower Ni contamination, better crystallinity, and higher crystalline fraction than MILC poly-Si films. The p-channel SILC poly-Si TFTs exhibited a mobility of 66 cm2/V·s, a minimum leakage current of 3.4 × 10−11 A at VD = −5 V, a subthreshold slope of 0.85 V/dec, and a maximum on/off ratio of 5.0 × 106, all of which resulted in a high-performance device which surpassed conventional MILC poly-Si TFTs.

Application of nano-pulsed Nd:YAG laser to crystallization of amorphous Si thin films for next generation flat-panel display

A 532nm Nd:YAG laser was applied to crystallize amorphous Si thin films in order to evaluate the applicability of Nd:YAG laser to low-temperature polycrystalline Si technology. In this study, we aim at enhancing uniformity as well as crystallinity. In order to achieve the goal, a new optical system called as a diffusing system was used to enhance the uniformity of irradiating beam profile, consequently improving the quality of crystallized microstructures. Optimal processing parameters for high crystallinity and uniformity were developed by design of experiments (DOE). To investigate crystallinity and uniformity, Raman spectroscopy and optical microscopy were utilized. Therefore, the effectiveness of Nd:YAG laser is suggested as a feasible alternative that is capable of crystallizing the amorphous Si thin films.

The Electrical Properties of Low Temperature Polycrystalline Si Thin Film Transistor Prepared by Nickel-ALD Process

We have fabricated low temperature polycrystalline Si thin film transistors (LTPS TFTs) for flat panel displays. In this work, metal induced crystallization (MIC) using atomic layer deposition (ALD) was employed to obtain poly-Si as an active layer in LTPS TFTs. The small amounts of nickel atoms by ALD were deposited on amorphous Si to minimize the metal contaminations. The poly-Si thin films have large and uniform grains with average size of 27 um by self-limited reaction process of ALD. The n-type LTPS TFT exhibits a high field effect mobility of about 76 cm^2/Vs, a sub-threshold slope of 0.09 V, a threshold voltage of 4.79 V, and an on-off ratio of 4.9 x 10^6

Application of Modified Rapid Thermal Annealing to Doped Polycrystalline Si Thin Films Towards Low Temperature Si Transistors.

Modified thermal annealing was applied to the activation of the polycrystalline silicon films doped as p-type through implantation of <TEX>$B_2H_6$</TEX>. The statistical design of experiments was successfully employed to investigate the effect of rapid thermal annealing on activation of polycrystalline Si doped as p-type. In this design, the input variables are furnace temperature, power of halogen lamps, and alternating magnetic field. The degree of ion activation was evaluated as a function of processing variables, using Hall effect measurements and Raman spectroscopy. The main effects were estimated to be furnace temperature and RTA power in increasing conductivity, explained by recrystallization of doped ions and change of an amorphous Si into a crystalline Si lattice. The ion activation using rapid thermal annealing is proven to be a highly efficient process in low temperature polycrystalline Si technology.

Evaluation of poly-Si thin film crystallized by solid green laser annealing using UV/visible Raman spectroscopy

Depth and in-plane distributions of the crystal qualities in low-temperature polycrystalline Si (LTPS) films fabricated by green laser annealing with s and p-polarizations and commercial excimer laser annealing were evaluated by Raman spectroscopy with UV and visible excitation laser sources from the front and back surfaces. A quasi-line excitation source provides a one-dimensional profile with 200-nm spatial resolution and step-by-step scanning parallel to the quasi-line to obtain two-dimensional mapping images. The Raman peak shift corresponds to the residual stress in the film, and the full width at half-maximum (FWHM) indicates the crystallinity. Both were analyzed using the mapping images and one-dimensional profiles. Crystal quality and residual stress as measured by the Raman peak shift and crystallinity as indicated by FWHM significantly depended on the annealing conditions. The depth profile was also unique to each sample. These results show that Raman mapping using UV and visible excitation sources is very useful for evaluating the crystal quality of LTPS films.

Application of 532 nm YAG-Laser Annealing to Crystallization of Amorphous Si Thin Films Deposited on Glass Substrates

A 532 nm Nd-YAG laser was applied to crystallize amorphous Si thin films in order to evaluate the applicability of a Nd-YAG laser to low-temperature polycrystalline Si technology. The irradiation of a green laser was controlled during the crystallization of amorphous Si thin films deposited onto glass substrates in a sophisticated process. Raman spectroscopy and UV-Visible spectrophotometry were employed to quantify the degree of crystallization in the Si thin films in terms of its optical transmission and vibrational characteristics. The effectiveness of the Nd-YAG laser is suggested as a feasible alternative that is capable of crystallizing the amorphous Si thin films.

Local resistance measurement across grain boundaries in low-temperature polycrystalline silicon layer of thin film transistor using scanning spreading resistance microscopy

Local resistance distribution in a low-temperature polycrystalline Si layer of a thin film transistor with a lightly doped drain (LDD) structure was investigated using scanning spreading resistance microscopy. The local resistance around the grain boundaries was found to be lower than that at grain insides in the drain, LDD, and channel regions. At the center of the grain boundaries, however, slightly higher resistance part was sandwiched between low resistance regions. Identifying the drain, the LDD, and the channel regions is succeeded by an analysis in which only the lower local resistances were used.

Effect of H2 on polycrystalline Si films deposited by plasma-enhanced CVD using Ar-diluted SiH4

Low-temperature polycrystalline Si films were fabricated by radio frequency plasma-enhanced chemical vapor deposition using SiH4, Ar and H2 as source gas. It was found that the content of H2 in the mixture plays an important role for crystallization of Si films. High-quality low-temperature polycrystalline Si films were obtained under the optimal amount of H2 in the source gas.

Directional thermoelectric properties of Ru 2Si 3

The orthorhombic compound Ru 2Si 3 is currently of interest as a high-temperature thermoelectric material. In order to clarify the effects of crystal orientation on the thermoelectric properties of Ru 2Si 3, we have examined the microstructure, Seebeck coefficient, electrical resistivity, and thermal conductivity of Ru 2Si 3 along the three principal axes, using these measured quantities to describe the relative thermoelectric performance as a property of crystal orientation. Ru 2Si 3 undergoes a high temperature (HT)→low temperature (LT) phase change and polycrystalline Si platelet precipitation during cooling, both of which are expected to effect the thermoelectric properties. The HT tetragonal→LT orthorhombic phase transformation results in a [010]//[010], [100]//[001] two-domain structure, while polycrystalline Si precipitation occurs on the (100) LT and (001) LT planes. The [010] orientation is found to posses superior thermoelectric properties (with the dimensionless figure of merit, ZT [010]/ZT [100]>4 at 900 K), due principally to the larger Seebeck coefficient along the [010] direction. The effect of the domain structure on the thermoelectric properties is discussed.

Directional Thermoelectric Performance of Ru2Si3

ABSTRACTThe orthorhombic compound Ru2Si3 is currently of interest as a high-temperature thermoelectric material. In order to clarify the effects of crystal orientation on the thermoelectric properties of Ru2Si3, we have examined the microstructure, Seebeck coefficient, electrical resistivity, and thermal conductivity of Ru2Si3 along the three principal axes, using these measured quantities to describe the relative thermoelectric performance as a property of crystal orientation. Ru2Si3 undergoes a high temperature (HT)→low temperature (LT) phase change and polycrystalline Si platelet precipitation during cooling, both of which are expected to effect the thermoelectric properties. The HT tetragonal→LT orthorhombic phase transformation results in a [010]//[010], [100]//[001] two-domain structure, while polycrystalline Si precipitation occurs on the (100)LT and (001)LT planes. The [010] orientation is found to posses superior thermoelectric properties (with the dimensionless figure of merit, ZT[010]/ZT[100]&gt;4 at 650°C), due principally to the larger Seebeck coefficient along the [010] direction. The effect of the domain structure on the thermoelectric properties is discussed.

Location control of crystal grains in excimer laser crystallization of silicon thin films

Location of crystal grains in polycrystalline Si thin films formed by excimer-laser crystallization is controlled by manipulating the superlateral-growth phenomenon. The superlateral growth of a single grain occurs preferentially at an artificial site where nanometer-sized crystallites are embedded in the precursory amorphous thin films. Only a part of the crystallites embedded in the site could survive the melting and grow to serve as the seed crystal in the subsequent recrystallization. Such grain-location control provides a basis for two-dimensional control of the grain-boundary location in low-temperature polycrystalline Si thin films, which is essential to the device-to-device uniformity of high-performance thin-film transistors.