Low Temperature Polysilicon Thin Film Research Articles

Highly Robust Flexible Poly-Si Thin Film Transistor Under Mechanical Strain With Split Active Layer for Foldable Active Matrix Organic Light Emitting Diode Display

We report a novel active split structure of low-temperature polysilicon (LTPS) thin film transistor (TFT) on polyimide (PI) substrate showing robust electrical performance under mechanical strain. The compressive and tensile bending tests were carried out with cylinders of radii 3, 2 and 1 mm respectively. The active split TFT exhibits much more stable electrical performance than the conventional TFT. The conventional LTPS TFT shows electrical failure due to the crack generation during tensile or compressive bending test carried out with 1 mm radius cylinder. The split poly-Si islands could resist crack formation/propagation, resulting in a robust electrical performance.

P‐15.4: A newly Integrated Ambient Light sensor with full in‐cell structure

In this paper, we present a novel integrated light‐dependent sensor which can be used to detect the illuminance of the ambient light. Based on the low temperature polysilicon (LTPS) thin film transistor (TFT) process and photosensitivity of a‐Si, the sensor can realize 0‐10K lux of the monitor range and 0.5 lux/step. It saves more space for terminal devices which will also facilitates the full screen display.

Strain distribution and electrical characteristics of flexible low-temperature polysilicon thin film transistors under biaxial bending

This paper investigates the strain distribution of flexible p-channel low temperature polycrystalline silicon thin film transistors under biaxial bending. The strain distribution of LTPS TFTs under different bending conditions is analysed by finite element analysis. \U0001d6c6r and \U0001d6c6θ are essentially equal and constant within the load ring. The finite element analysis shows that when the biaxial bending strain condition is 2.5%, the strain distribution is mainly concentrated at the contact angle between the electrode and the oxide layer. This strain is significantly greater than the overall strain of the device, which is the main reason for the bending performance of the device. We found that under biaxial bending, the threshold voltage shifts towards the negative axis as the biaxial strain increases. Within this strain range, these electrical properties are evident under biaxial strain conditions. Comparing theoretical threshold voltage shifts based on energy band changes with experimental results under biaxial strain, it was found that changes in trap density should also contribute to the threshold voltage shift.

Study of traps in low-temperature polysilicon thin film transistors using a current transient method

The trap characteristics of low-temperature polysilicon thin film transistors (TFTs) are studied using a current transient method that is based on the trapping and detrapping of charge carriers from the trap sites in the device. Analysis of the measured current transient curve allowed three types of detrapping behavior to be identified, each of which displayed a different time constant, activation energy, and spatial position. This current transient method can be integrated into the negative bias temperature instability stress test used for the reliability study. The peak amplitudes of the traps increase because of the stress applied in the test, thus demonstrating that the degradation mechanism of the TFTs is closely related to changes in the traps in these devices.

Comparative study of C–V-based extraction methods of interface state density for a low-temperature polysilicon thin film

To extract comprehensive and accurate interface state density (D it) distribution for a low-temperature polysilicon (LTPS) thin film, three well-established methods based on capacitance–voltage (C–V) measurements were compared: high–low frequency capacitance, conductance, and quasi-static (QS) capacitance methods. Because of the strong frequency-dependent response of grain boundary traps within the LTPS, C–V measurements are necessary on p- as well as n-type LTPS films, as they provide D it distribution across the entire LTPS band gap. The QS capacitance method, which uses an optimal high-frequency C–V curve with a minimal grain boundary trap response, provided the best and most comprehensive estimate of D it distribution across the LTPS band gap, even at room temperature (25 °C). Although the narrow extraction ranges of D it were extended toward the mid-gap region by increasing the measurement temperature in both high–low frequency capacitance and conductance methods, the responses of the grain boundary traps still overestimated the D it values near the band edges.

A Self-Refreshing Memory-in-Pixel Comprising Low Temperature Poly-Silicon and Oxide TFTs for 3-Bit Liquid Crystal Displays

In this letter, a self-refreshing multi-level memory-in-pixel (MIP) circuit for liquid crystal display (LCD) comprising low temperature poly-silicon and oxide (LTPO) thin film transistors (TFTs) is proposed. Since the proposed MIP circuit features self-refreshing without embedding frame memory, power consumption can be minimized when displaying a still image. Measurement results verify that the proposed circuit successfully enables a 3-bit grayscale. The LCD employing the proposed MIP circuit consumes only 1.22 % of power compared with a conventional LCD when displaying a still image. Thus, the proposed multi-level MIP circuit is expected to enable a low-power LCD featuring higher color depth with a simple structure.

(Invited) Integration of Organic Photodiode with Low Temperature Poly Silicone Thin Film Transistors for a Conformable Image Sensor

With the rapid aging of Japanese society, how to increase quality of life (QoL) while controlling rising medical expenses has become an urgent issue. To solve this difficult issue, the acquisition and utilization of biological information using new technologies such as wearable devices is more expected. In particular, self-care and home medical care, in which patients and their families are responsible for their own health, are considered as one of the way to solving the issues of a super-aging society. Indeed, wearable sensors that can constantly monitor health conditions and home-use blood pressure monitors with communication functions are being introduced to the market one after another to prepare for the advent of a self-care era.On the other hand, when designing a new insurance system or incentive system using biometric information from wearable sensors, it is important issue how to confirm whether data measured at home is the patient's own. Furthermore, the risk of patient mix-ups must be reduced as more wearable devices come to be used in hospitals and welfare facilities in the future. Therefore, measuring vital signs simultaneously with biometric authentication of the user is an urgent issue.We have developed a sheet-type image sensor that enables high-resolution and high-speed reading. This sheet-type image sensor can take the high-resolution image of fingerprints and veins used for biometric authentication. In addition, the same sheet-type imager can measure the pulse wave which is one of the vital signs, and its distribution.Although there are many reports of sheet-type image sensors, it has not been achieved both high-resolution imaging and high-speed readout, and static biometric data and dynamic vital signs cannot be measured by one sheet-type image sensor. This is because high-sensitivity photodetectors and high-speed switching elements could not be integrated on a polymer substrate without damaging of the switching elements.The developed sheet-type image sensor is fabricated by densely integrating a high-efficiency readout circuit using an active matrix of a low-temperature polysilicon thin film transistor and a photodetector that uses a highly efficient organic semiconductor as a photosensitive layer. The resolution of the image sensor achieves 508 dots per inch (dpi) required for fingerprint authentication, and the organic photodetector consists of bulk hetero structure organic layer which has high photosensitivity to near infrared light with a wavelength of 850 nanometers (external quantum efficiency of 50% or more). It it easy to integrate the sheet-type image sensor into equipment and attach it to curved surfaces due to the thickness of the polymer base material is 10 micrometers, and the total thickness of the sheet-type image sensor is 15 micrometers (Figure 1). By developing a process technology that integrates photodetectors and thin-film transistors without damage to each other, it has become possible to realize a sheet-type image sensor that achieves both high-resolution imaging and high-speed reading.Evaluation of vein and fingerprint images taken by this sheet-type image sensor showed that the contrast difference of the veins was less than 5% compared to images using a general CMOS imager. We confirmed that the conformable imager has high image quality equivalent to that of conventional CMOS imagers.Since the sheet-type image sensor is thin and bendable, it can be easily integrated into wearable devices, and it is possible to measure health condition and perform biometric authentication at the same time. As a result, it is expected that prevention of “spoofing” and patient from being mixed up.

Effect of NBTI on the Electrical Characteristics and Trap States of Low Temperature Poly-silicon Thin Film Transistor

Polysilicon thin film transistors have broad application prospects in high-performance flat panel displays and flexible wearable devices due to their high carrier mobility and good stability. However, due to process conditions and other reasons, there are traps inside, and under some electrical stress conditions, its electrical properties will degrade. Here we report the changes in electrical characteristics of p-type polysilicon thin film transistors with stress time at a negative gate voltage of -20V and a temperature of 60°C. It is obtained that the transfer characteristics of the p-type polysilicon thin film transistor move in the negative direction with the increase of Negative Bias Temperature Instability time, and with the increase of SS degradation, and the total trap state inside it is calculated by SS, which provides a theoretical basis for improving the reliability of the device.

Abnormal hysteresis formation in hump region after positive gate bias stress in low-temperature poly-silicon thin film transistors

Degradation in low-temperature polycrystalline-silicon thin-film transistors after electrical stress was thoroughly investigated in this work. Main channel degradation, abnormal hump generation and hysteresis appearing in the hump region can be observed after positive bias stress. Furthermore, the difference in subthreshold swing (SS) values between forward/reverse sweep is observed. The electron trapping into the gate insulator (GI) dominates the main degradation and the hump generation. Additionally, the difference in SS values which appears in the hump region is attributed to the interface traps and the hysteresis is caused by electron trapping/detrapping into GI.

A Memory-in-Pixel Circuit for Low-Power Liquid Crystal Displays With Low Temperature Poly-Silicon and Oxide Thin Film Transistors

We propose a new memory-in-pixel (MIP) circuit using low temperature poly-silicon and oxide (LTPO) thin film transistors (TFTs) to achieve the high reliability as well as low power consumption. The proposed pixel circuit can greatly reduce the frame frequency due to extremely low leakage current of oxide TFTs. Moreover, the driving TFTs of the circuit can be stable under continuous stress for a long period of time because low temperature poly-silicon TFTs show high reliability. The pixel is driven directly by applying black or white voltage so that a flicker can be minimized. Fabricated circuit successfully verifies the circuit performance under the frame frequency of 1/60 Hz and the polarity inversion frequency of 0.5 Hz. Therefore, we expect that our proposed MIP circuit can provide flicker-free liquid crystal displays featuring low power consumption as well as high reliability.

Thermal conductive hybrid polyimide with ultrahigh heat resistance, excellent mechanical properties and low coefficient of thermal expansion

It is a great challenge to fabricate flexible substrate materials with an ultrahigh heat resistance, low coefficient of thermal expansion (CTE) and high thermal conductivity, which is required to process low temperature poly-silicon thin film transistors in active matrix organic light-emitting-diode devices. Despite the development of new monomers is also possible to simultaneously improve the heat resistance and dimensional stability of polyimides, the space for improvement is limited and the cost is greatly increased. Traditional polymer nanocomposites can increase the glass transition temperature (Tg) and reduce the CTE, but they cause a significant drop in mechanical properties. Herein, an amino-functionalized boron nitride nanosheets (BNNS_APS) hybrid polyimide (PI) was prepared by in situ polymerization. The hybrid PI exhibited ultrahigh heat resistance, excellent thermal conductivity, low CTE and good mechanical properties with 1 wt% BNNS_APS doping. The Tg of the hybrid PI was improved up to 473 °C and the thermal conductivity was increased by 100% compared with pure PI. The CTE was less than 7 ppm/K, and the tensile strength and elongation at break increased to 336 MPa and 16.6%, respectively. These results are attributed to the good dispersion of BNNS_APS in the PI matrix and the strong interactions between the BNNS_APS and PI chains. The mechanism was proposed and discussed in detail.

P‐1.6: Highly Stable LTPS TFT on Si Wafer under High Current Stress

In this work, we report low temperature polysilicon (LTPS) thin film transistor (TFT) on the glass substrate and silicon wafer substrate by using blue laser annealing (BLA). The TFTs evaluated the high current stress (HCS) at the gate voltage (VGS) ‐20 V and the drain voltage (VDS) ‐6 V for 1 h. As a result, the performance of TFT on the silicon wafer shows excellent stability of HCS compared to that of TFT on the glass substrate. Also, viewed in its entirety, the break down current (IBK) of glass sample smaller than silicon wafer sample at breakdown voltage.

Gate Modulation of Excitatory and Inhibitory Synaptic Plasticity in a Low-Temperature Polysilicon Thin Film Synaptic Transistor

Neuromorphic computing with intelligent power-efficient data processing has become an innovative technology to overcome the performance bottleneck of traditional von Neumann-type computing architecture. As an essential element to construct a neuromorphic system, a kind of artificial synapse with high technology maturity, rich functionality, and homeostatic regulation based on simple and robust mechanism is in urgent demand. Here, we propose the dual-gate low-temperature polycrystalline silicon thin film transistor to be a prospective candidate for scalable biomimetic synapse. Fundamental bilingual homosynaptic behaviors, including excitatory postsynaptic current, inhibitory postsynaptic current, and paired pulse facilitation, have been successfully emulated based on the charge trapping mechanism under electric pulse stimulation at either top or bottom gates. The strength of the top-gated induced excitatory and inhibitory responses can be dynamically modulated by the electrical biases at the modulatory bot...

The Oxide TFT with Solution Based Gate Insulator

Low temperature poly-Silicon (LTPS) thin film transistor (TFT) and Oxide TFT are developed for the better performance of the active matrix display. Recently, oxide TFT has been investigated intensively due to simple process and higher mobility than amorphous silicon TFT. Typical parameters of TFT are mobility, threshold voltage and On/Off ratio which are influenced by gate insulator. The widely used material for gate insulator is SiO2 which is rich in the earth and inexpensive. But vacuum equipments like the plasma enhanced chemical vapor deposition (PECVD) and the RF Magnetron sputter need large investment and maintenance cost than non-vacuum process. Oxide TFT of top gate structure reduces the parasitic capacitance between source-drain and gate metal. The plasma damage during deposition of gate insulator on an oxide active layer cause the defects which deteriorate TFT characteristics. However, the gate insulator by solution process reduces the defects by plasma process. SU-8 which is a negative photoresist (PR) has been being used widely in micro electro mechanical system (MEMS). It is constituted with octuple epoxy groups and includes photosensitize to react with UV light. The polymer network generated by cross-linking has mechanical and chemical stabilities and high electrical resistance. In this experiments, SU-8 was used for the gate insulator of the oxide TFT and investigated the effect of the SU-8 gate insulator on the oxide TFT. In this paper, we investigated the characteristics of gate insulator of SU-8 as changing UV exposure time to SU-8. SU-8 was coated by spin coating with 2000 rpm on a p-type Si wafer. After soft-bake for 1.5 min at 95˚C, UV of 365 nm was exposed at an energy of 320mJ/s. Exposure times were varied as 30s, 60s, 120s, and 240s. After UV exposure, hard bake was done for 20 min at 115˚C. An Al layer was deposited on SU-8, and electrical properties of the SU-8 were measured after post-annealing. Figure 1 shows the current densities of the SU-8 insulators for various exposure time from 30s to 240s. As shown in Fig. 1, the leakage currents decreased as the exposure time increased from 30s to 240s. For the gate insulator of the oxide TFT, the proper UV exposure is important. Figure 1

Poly‐Si active matrix organic light‐emitting diode pixel circuit with compensation for threshold voltage and mobility variations

A new pixel circuit and driving method for large-area, high-luminance active matrix organic light-emitting diode (AMOLED) displays were studied to improve the image quality. The AMOLED display was designed with low-temperature poly-silicon thin film transistors (TFTs), which have good stability but poor uniformity. To overcome the uniformity problem, the proposed pixel circuit compensates for variations in the threshold voltage and the mobility of the driving TFT. The proposed pixel circuit can operate in two compensation modes for high-luminance operation; and the black data insertion was introduced to improve the characteristics of moving images. The pixel circuit was designed for an 11.6″WXGA top-emission AMOLED panel, and its non-uniformity was estimated to be < 4% with a mobility compensation time of 1 μs.

An ambient-light sensor system with startup correction for LTPS-TFT LCD

An ambient-light sensor system using low-temperature poly-silicon thin film transistors was studied, to reduce the power consumption of mobile applications. The proposed system with startup correction can correct the panel-to-panel variation of the ambient-light sensors, without additional equipment. The digital output of the readout circuit has 8 levels per decade for the input luminance ranges from 100 to 10000lux, and the readout rate is 40Hz. The proposed method provides maximum differential non-uniformity below 0.3 LSB.

Investigation of the instability of low-temperature poly-silicon thin film transistors under a negative bias temperature stress

In this work, we analyzed and correlated the hysteresis characteristics and instability under negative bias temperature instability (NBTI) stress in p-channel low-temperature poly-silicon (LTPS) thin-film transistors (TFTs). Positive VTH shifts were observed under the NBTI stress. The hysteresis does not appear to be affected by the NBTI stress; however, when the VG stress voltage is −40 V at 100°C, the hysteresis increases as the stress time increases and VTH shifts with sub-threshold slope (SS) degradation. The hysteresis may increase under the extreme stress condition due to the generation of trap-states.

Flexible PVDF-TrFE pyroelectric sensor driven by polysilicon thin film transistor fabricated on ultra-thin polyimide substrate

In this work we present a flexible pyroelectric sensor composed by a PVDF-TrFE capacitor realized on ultra-thin polyimide film (5μm thick), integrated with a n-channel low temperature polysilicon thin film transistor also fabricated on ultra-thin polyimide (8μm thick). Exploiting a multi-foil approach, the pyroelectric capacitors and the transistors were attached one over the other reaching a final thickness of about 15μm. The bottom contact of the sensor capacitance was connected to the gate of the transistor by a silver ink, while, for bias and load resistances, we used external elements. The active sensor area was defined by a circular capacitor with a diameter of about 2mm. In order to enhance PVDF-TrFE pyroelectric properties, an external stepwise voltage was applied to the structure up to values of 160V at a temperature of about 80°C. The devices were then tested, at different working frequencies (up to 800Hz) under a specific infrared radiation provided by a He–Ne laser, with a wavelength of 632nm and maximum power of 5mW. An output signal of tens of millivolt was observed at 10Hz, exploiting the pre-amplification of polysilicon thin film transistor.

Electrical Characteristic Analysis Using Low-Frequency Noise in Low-Temperature Polysilicon Thin Film Transistors

This study carried out an electrical characteristic analysis using low-frequency noise (LFN) in top gate p-type low-temperature polysilicon thin film transistors (LTPS TFTs) with different active layer thicknesses between 40 nm and 80 nm. The transfer characteristic curves show that the 40-nm device has better electrical characteristics compared with the 80-nm device. The carrier number fluctuation, with and without correlated mobility fluctuation model in both devices, has modeled well the measured noise. On the other hand, the trap density and coulomb scattering in the 40-nm device are smaller compared with the 80-nm device. To confirm the effectiveness of the LFN noise analysis, the trap densities at a grain boundary are extracted using in both devices the similar methods of Proano et al. and Levinson et al. That is, coulomb scattering, caused by the trapped charges at or near the interface, has a greater effect on the device with inferior electrical properties. Based on the LFN and the quantitative analysis of the trap density at a grain boundary, the interface traps between the active layer and the gate insulator can explain the devices' electrical degradation.

The low temperature polysilicon (LTPS) thin film MOS Schottky diode on glass substrate for low cost and high performance CO sensing applications

The Au/SnO 2/n-LTPS MOS Schottky diode prepared on a glass substrate for carbon monoxide (CO) sensing applications is studied. The n-LTPS (n-type low temperature polysilicon) is prepared by excimer laser annealing and PH 3 plasma treatment of an amorphous Si thin film on glass substrate. The developed Schottky diode exhibits a high relative response ratio of ∼546% to 100 ppm CO ambient under condition of 200 °C and −3 V bias. The response ratio is better than the reported SnO 2 based resistive type CO sensors of 100% and 37%, respectively on poly-alumina and glass substrates or comparable to 390% of Pt-AlGaN/GaN Schottky diode CO sensor. Thus, the Au/SnO 2/n-LTPS Schottky diode has the potential to develop a low cost high performance CO sensor.