Low-temperature Polysilicon Thin-film Transistors Research Articles

TMCTS for gate dielectric in thin film transistors

AbstractThe use of the liquid source tetramethylcyclotetrasiloxane (TMCTS) for gate dielectric deposition in low-temperature polysilicon thin film transistor (TFT) processes is investigated. TMCTS was reacted with O2 in an LPCVD furnace at 580°C to form a gate dielectric. For comparison, a low temperature oxide (LTO) was deposited as a gate dielectric using SiH4−O2 LPCVD at 450°C. Capacitance and charge pumping measurements indicate fewer interface states for TMCTS gate dielectric. Both NMOS and PMOS TFTs show comparable or superior performance with TMCTS oxide. Post-deposition annealing has less effect on TMCTS gate oxides. Although TMCTS gate dielectrics appear slightly more susceptible to damage in biastemperature stress tests, TFTs with TMCTS gate oxides still retain better performance after stressing.

Conduction behaviour of low-temperature (≤600°C) polysilicon TFTs with an in situ drain doping level

The electrical properties of low temperature (≤600°C) polysilicon thin film transistors (TFTs) are investigated as a function of temperature and drain and gate voltage. Two types of TFTs have been processed: Classical in situ Doped Drain TFTs (CDD TFTs) and Lightly in situ Doped Drain TFTs (LDD TFTs). The electrical properties of the TFT can be improved by a reduction of the in situ drain doping level. For instance the OFF state current can be significantly reduced at low drain voltage ( V ds<5 V) owing to a reduction of the local electrical field near the drain. Therefore LDD TFTs exhibit a high ON/OFF state current ratio ( I ON I OFF =4 × 10 6 ). For both TFTs the ON state current is well described by the trapping of carriers at grain boundaries located near the interface. In addition for both structures the OFF state current ( I OFF) results from various processes of trapped carrier emission at grain boundaries localized in the space charge region of the drain junction, such as pure thermal emission, Poole-Frenkel thermal emission, thermoelectronic field emission, and band to band tunneling emission.

Comparison of the low-temperature ( ≤ 600 °C) polysilicon thin-film transistors (TFTs) with two kinds of gate dielectrics

Low-temperature ( ≤ 600 °C) polysilicon thin film transistors (TFTs) were processed with two types of gate insulator: wet oxide/LPCVD Si 3N 4 double layer and APCVD SiO 2 thin film. Electrical performances were analyzed and compared for the two types of TFT. The thermal oxide with LPCVD Si 3N 4 thin film provides a better gate insulator/poly-Si interface than the gate APCVD SiO 2 insulator in terms of effective interface state density, which is approximately ten times lower ( N T = 9 − 10 × 10 11 cm −2 eV −1 versus 8 − 9 × 10 12 cm −2 eV −1), and in terms of field effect mobility, which is much higher (μ = 58 cm 2 V −1 s −1 versus 6 cm 2 V −1 s −1). However, the threshold voltage is higher ( V T = 6.5 V versus 5 V) because of a hot carrier trapping effect at the SiO 2 Si 3N 4 interface. In addition, gate insulation with oxide/nitride is not as good as with APCVD SiO 2.

High performance low temperature polysilicon thin film transistor using ECR plasma thermal oxide as gate insulator

Electron cyclotron resonance (ECR) plasma thermal oxide has been investigated as a gate insulator for low temperature (/spl les/600/spl deg/C) polysilicon thin-film transistors based on solid phase crystallization (SPC) method. The ECR plasma thermal oxide films grown on a polysilicon film has a relatively smooth interface with the polysilicon film when compared with the conventional thermal oxide and it shows good electrical characteristics. The fabricated poly-Si TFT's without plasma hydrogenation exhibit field-effect mobilities of 80 (60) cm/sup 2//V/spl middot/s for n-channel and 69 (48) cm/sup 2//V/spl middot/s for p-channel respectively when using Si/sub 2/H/sub 6/(SiH/sub 4/) source gas for the deposition of active poly-Si films.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

High Mobility Non-Hydrogenated Low Temperature Polysilicon TFTs

AbstractWe have fabricated polysilicon (poly-Si) thin film transistors (TFTs) using a standard 4-mask sequence, with self-aligned ion implantation for source and drain doping. The active layer was obtained by solid phase crystallisation of high purity Si2H6-deposited amorphous Si, whereas the gate oxide was synthesised by a novel plasma deposition technique, namely distributed electron cyclotron resonance plasma enhanced chemical vapour deposition (DECR PECVD). We have obtained high carrier mobilities (70 cm2V−1s−1 for electrons and 40 cm2V−1s−1 for holes) with an excellent uniformity and without the need for a post-hydrogenation treatment. Moreover, we show that the TFT characteristics are practically insensitive to hot carrier effects.

Low-temperature polysilicon TFT with gate oxide grown by high-pressure oxidation

Polysilicon thin-film transistors (TFTs) were fabricated with the maximum processing temperature limited to 650 degrees C. Best results were obtained when the gate oxide was grown by a two-step high-pressure oxidation process, using high-pressure steam and then dry oxygen both at 15 atm and 650 degrees C. The TFTs exhibit a mobility of 34 cm/sup 2//V*s, threshold voltage of 3.5 V, leakage current below 0.01 pA/ mu m, subthreshold slope of 0.18 V/decade, and an ON/OFF ratio of over eight orders of magnitude. These values are comparable to those obtained with conventional polysilicon TFTs using high-temperature thermal oxidation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Low-temperature polysilicon TFT with two-layer gate insulator using photo-CVD and APCVD SiO/sub 2/

The performance of polysilicon thin-film transistors (TFTs) formed by a 600 degrees C process was improved using a two-layer gate insulator of photochemical-assisted vapor deposition (photo-CVD) SiO/sub 2/ and atmospheric-pressure chemical vapor deposition (APCVD) SiO/sub 2/. The photo-CVD SiO/sub 2/, 100 AA thick, was deposited on polysilicon and followed by APCVD SiO/sub 2/ of 1000 AA thickness. The TFT had a threshold voltage of 8.3 V and a field-effect mobility of 35 cm/sup 2//V-s, which were higher than those of the conventional TFT with a single-layer gate SiO/sub 2/ of APCVD. Hydrogenation by hydrogen plasma was more effective for the new TFT than for the conventional device. >