Low-temperature Epitaxial Growth Research Articles

Low-Temperature Growth of InGaAs Quantum Wells Using Migration-Enhanced Epitaxy.

The growth of InGaAs quantum wells (QWs) epitaxially on InP substrates is of great interest due to their wide application in optoelectronic devices. However, conventional molecular beam epitaxy requires substrate temperatures between 400 and 500 °C, which can lead to disorder scattering, dopant diffusion, and interface roughening, adversely affecting device performance. Lower growth temperatures enable the fabrication of high-speed optoelectronic devices by increasing arsenic antisite defects and reducing carrier lifetimes. This work investigates the low-temperature epitaxial growth of InAs/GaAs short-period superlattices as an ordered replacement for InGaAs quantum wells, using migration-enhanced epitaxy (MEE) with low growth temperatures down to 200-250 °C. The InAs/GaAs multi-quantum wells with InAlAs barriers using MEE grown at 230 °C show good single crystals with sharp interfaces, without mismatch dislocations found. The Raman results reveal that the MEE mode enables the growth of (InAs)4(GaAs)3/InAlAs QWs with excellent periodicity, effectively reducing alloy scattering. The room temperature (RT) photoluminescence (PL) measurement shows the strong PL responses with narrow peaks, revealing the good quality of the MEE-grown QWs. The RT electron mobility of the sample grown in low-temperature MEE mode is as high as 2100 cm2/V∗s. In addition, the photoexcited band-edge carrier lifetime was about 3.3 ps at RT. The high-quality superlattices obtained confirm MEE's effectiveness for enabling advanced III-V device structures at reduced temperatures. This promises improved performance for applications in areas such as high-speed transistors, terahertz imaging, and optical communications.

Low temperature epitaxial growth of Cantor-nitride thin films by magnetic field assisted magnetron sputtering

Low-temperature epitaxial growth of multicomponent alloy-based thin films remains an outstanding challenge in materials science and is important for established fundamental properties of these complex materials. Here, Cantor nitride (CrMnFeCoNi)N thin films were epitaxially grown on MgO(100) substrates at low deposition temperature by magnetic-field-assisted dc-magnetron sputtering, a technique where a magnetic field is applied to steer the dense plasma to the substrate thereby influencing the flux of Ar-ions bombarding the film during growth. Without ion bombardment, the film displayed textured growth. As the ion flux was increased, the films exhibited epitaxial growth. The epitaxial relationship between film and substrate was found to be cube on cube (001)film||(001)MgO, [100]film||[100]MgO. The epitaxy was retained up to a thickness of approximately ∼100 nm after which the growth becomes textured with a 002 out-of-plane orientation. The elastic constants determined by Brillouin inelastic light scattering were found to be C11 = 320 GPa, C12 = 125 GPa, and C44 = 66 GPa, from which the polycrystalline Young’s modulus was calculated as 204 GPa and Poisson's ratio = 0.32, whereas available elastic properties still remained very scarce.

Ferroelectric Hf0.5Zr0.5O2 films with improved endurance obtained through low temperature epitaxial growth on seed layers.

Crystallization temperature is a critical parameter in the stabilization of the metastable ferroelectric phase of HfO2. The optimal crystallization temperature used for polycrystalline films is too low to grow epitaxial films. We have developed a new growth strategy, based on the use of an ultrathin seed layer, to obtain high-quality epitaxial films of orthorhombic Hf0.5Zr0.5O2 at a lower temperature. The threshold temperature for epitaxy is reduced from about 750 °C to about 550 °C using a seed layer. Epitaxial films deposited at low temperatures exhibit highly enhanced endurance, and films grown at 550-600 °C show high polarization, no wake-up effect, and greatly reduced fatigue and improved endurance in comparison with the films deposited at high temperatures without a seed layer. We propose that the endurance enhancement is due to a positive effect of the defects, which limits the propagation of pinned ferroelectric domains.

Pixel device based on a quantum well: Preliminary results on gate dielectrics

The development of pixel arrays close to the interaction point in large detector systems used in high energy physics require high radiation hardness for the pixels and their readout. A pixel device based on a quantum well, called the DoTPiX uses a sensing n-channel MOS device with a control gate. A buried Ge layer acts as a current modulation gate, which localize holes generated by impinging particles. The DotPIX buried Ge gate is obtained by low temperature epitaxial growth of Ge on Si. We have started to study the different ways to achieve these prerequisites: the need for a low temperature budget to reduce the Ge and Si intermixing, which may be detrimental to the DoTPiX operation. The use of Si thermal oxide is investigated together with that of deposited oxide (Hafnium Oxide for example), which differs from the Silicon Dioxide. The possibility of a combination of thermal silicon dioxide and deposited oxides opens another possibility in this study.

Dilute cobalt doping induced low temperature epitaxial growth of fluorine-free MOD prepared GdBa2Cu3O7−z superconducting films

Chemical solution deposition is becoming one of the most promising routes toward cost-effective production of REBa2Cu3O7−z (REBCO) based high temperature superconducting tapes. However, a comprehensive understanding of nucleation and growth for REBCO films with dopants, especially considering low sintering temperature and high reproducibility, is still far from being achieved. In this work, dilute Co was introduced into fluorine-free precursor, and comparison studies of a set of pristine and doped GdBCO films were carried out. Correlation between texture, microstructure and critical current density were established, and nucleation & growth mechanism for doped films were proposed. By comparison, Co doping enables to reduce the textured temperature about 50 ℃ because of the dramatically decreased decomposition temperature of intermediate phase BaCO3, which facilitate Ba-Cu-O liquid phase transformation and thus GdBCO epitaxial growth at lower temperatures. These results bring particular opportunities for fine tuning of the film fabrication process by incorporating dilute impurities in precursors.

(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

The epitaxial growth of group IV semiconductor materials is one of the backbones of modern IC production flows. At present nodes it is used for the Source/Drain (S/D) engineering of both p- and n-MOS high performance transistors, allowing the deposition of SiGe:B and Si:P layers with active carrier concentrations ~ 1x1021 cm-3, ensuring low contact resistivities [1]. However, with reducing device dimensions, the growing importance of contact resistance in devices remains a major concern. A significantly lower parasitic S/D resistance could also be obtained thanks to the use of epitaxial and metal wrapped-around contacts (WAC) [2]. In addition, alternatives to Si channel materials (SiGe or Ge) and new device concepts such as 3D transistor stacking, complementary FET (CFET) and gate-all-around (GAA) nanosheet devices, all considered for the upcoming technological nodes of 3 nm and below [3], require process temperatures < 500ºC.To meet these temperature requirements, epitaxial processes based on the combination of high order Si and Ge precursors are explored together with low temperature Cl2 etching. The strength of this approach has already been demonstrated by the successful implementation of Ge/SiGe stacks and Ge S/D deposited at low temperature for the production of pMOS Ge GAA devices exhibiting excellent electrostatic control at sub-30 nm gate lengths [3].In this contribution, we use advanced low temperature epitaxial processes to enable cutting-edge applications. Complex and highly strained multi stacks are pseudomorphically grown with a limited thermal budget. The compositional contrast between the different parts of the stack, combined with very sharp interfaces, allows for the selective removal of sacrificial layers and the formation of active channels being totally isolated from parasitic channels in the substrate (Fig. 1(a)). In addition, highly B (Fig. 1 (b)) or B+Ga co-doped SiGe layers are grown at temperatures down to 400ºC with an active doping concentration exceeding 1x1021 cm-3. Epitaxial WAC structures are finally demonstrated Fig. 1 (c).[1] H. Wu et al., IEDM, 819 (2018)[2] S. Chew et al., 2017 IEEE Int. Interconnect Techn. Conf. (IITC), 1 (2017)[3] E. Capogreco, et al., Symposium on VLSI Technology , T94 (2019) Fig. 1. Example applications for advanced low temperature epitaxial growth processes. (a) HAADF-STEM cross-section image of a SiGe/Si multi stack used for the fabrication of nanosheet device with integrated bottom SiN/SiCO isolation; (b) B concentration profile measured by SIMS on a SiGe:B layer grown at low temperature, resulting in a carrier concentration above ~1x1021 cm-3. (c) Low temperature SiGe:B grown on Si fins demonstrating epitaxial WAC. Figure 1

(Invited) Cutting-Edge Epitaxial Processes for Sub 3 Nm Technology Nodes: Application to Nanosheet Stacks and Epitaxial Wrap-Around Contacts

This work reports on low temperature epitaxial growth solutions for the processing of advanced CMOS devices beyond the 3 nm technological node. The complex stacking of highly compositionally contrasted strained group IV materials is first demonstrated at 500°C. It enables the formation of active nanosheet channels with bottom isolation, necessary for ultimate transistor scaling. Using high order Si and Ge precursors also offers great opportunities for the epitaxy of advanced source/drain materials. It allows achieving hole active concentrations as high as 1.3x1021 cm-3 in in-situ B-doped Si0.5Ge0.5, providing Ti / SiGe:B contacts with low specific resistivity. Grown at temperatures as low as 400°C, the epilayers deposit in a conformal manner, thereby wrapping high aspect ratio 3-dimensional structures and maximizing the contact areas, being an additional option to further decrease device access resistances. As an alternative to B-doping only, we also demonstrate uniformly Ga-doped materials with concentrations ~ 1x1020 cm-3. B and Ga are finally combined to co-dope SiGe and further reduce the Ti / p-SiGe contact resistivity.

SrTiO3/Bi4Ti3O12 Nanoheterostructural Platelets Synthesized by Topotactic Epitaxy as Effective Noble-Metal-Free Photocatalysts for pH-Neutral Hydrogen Evolution.

Low-temperature hydrothermal epitaxial growth and topochemical conversion (TC) reactions offer unexploited possibilities for the morphological engineering of heterostructural and non-equilibrium shape (photo)catalyst particles. The hydrothermal epitaxial growth of SrTiO3 on Bi4Ti3O12 platelets is studied as a new route for the formation of novel nanoheterostructural SrTiO3/Bi4Ti3O12 platelets at an intermediate stage or (100)-oriented mesocrystalline SrTiO3 nanoplatelets at the completed stage of the TC reaction. The Bi4Ti3O12 platelets act as a source of Ti(OH)62– species and, at the same time, as a substrate for the epitaxial growth of SrTiO3. The dissolution of the Bi4Ti3O12 platelets proceeds faster from the lateral direction, whereas the epitaxial growth of SrTiO3 occurs on both bismuth-oxide-terminated basal surface planes of the Bi4Ti3O12 platelets. In the progress of the TC reaction, the Bi4Ti3O12 platelet is replaced from the lateral ends toward the interior by SrTiO3, while Bi4Ti3O12 is preserved in the core of the heterostructural platelet. Without any support from noble-metal doping or cocatalysts, the SrTiO3/Bi4Ti3O12 platelets show stable and 15 times higher photocatalytic H2 production (1265 μmol·g–1·h–1; solar-to-hydrogen (STH) efficiency = 0.19%) than commercial SrTiO3 nanopowders (81 μmol·g–1·h–1; STH = 0.012%) in pH-neutral water/methanol solutions. A plausible Z scheme is proposed to describe the charge-transfer mechanism during the photocatalysis.

Epitaxial Ge-on-Nothing Virtual Substrates for 3D Device Stacking Technologies

Future monolithic heterogeneous integration of Ge and IIIV materials in electronic, optoelectronic and photonic devices requires advanced layer transfer and 3D device stacking technologies, which starts with the fabrication of suitable (virtual) substrates. A layer transfer process based on the reorganization of macro-porous Si at high temperature was developed by imec [1]. The developed fabrication scheme to fabricate macropores is based on standard UV lithography and dry etching techniques rather than electrochemical etching. This enables an easy transfer to full Si wafers (up to 300 mm). During a high-temperature step, the top part of the macro-porous Si reflows. By using proper anneal conditions, the layer detaches from the mother substrate, being anchored by a few attachment points only, forming a ‘Si on nothing’ (SoN) stack (Fig. 1a). The suspended Si layer can then easily be transferred to another substrate.In this contribution, we assess the suitability of macro-porous Si and SoN as starting material for Ge virtual substrates. The goal is to provide a fabrication scheme that allows an easy detachment of the virtual substrate after wafer to wafer bonding. Macro-porous Si was only fabricated in the inner 10x10 cm2 area of 200 mm wafers using imec’s qualified fabrication scheme. Ge layers were simultaneously grown on the inner macro-porous Si (or SoN) and the outer bulk Si. This allows to compare the material properties without the risk of wafer to wafer variations due to non-reproducibility issues. Our approach for making macro-porous Si and SoN provides mono-crystalline, nearly defect-free, and extremely smooth Si starting surfaces. A standard low temperature epitaxial Ge growth process in an ASM-Epsilon® 2000 system was used to deposit the Ge layers [2].As an example, Fig. 1b shows a 1.25 mm thick mono-crystalline epitaxial Ge layer grown on a macro-porous Si layer. The Ge growth proceeds in a 2-dimensional mono-crystalline growth mode. The surface morphology of the grown Ge is not affected by the starting surface (Fig. 1c,d). The Full Width at Half Maximum (FWHM) as extracted from w-2q High Resolution X-ray Diffraction scans acquired around the Ge (004) Bragg peak is strongly reduced after a post Ge deposition anneal, which was also reported for Ge on bulk Si [2]. Threading dislocations annihilate during the post-epi anneal. FWHM values as low as 160 arc sec have been measured for 1.25 mm thick Ge layers independent of the underlying layer. This reflects the high material quality of the grown Ge. The difference in thermal expansion coefficient between Si and Ge results in some tensile stress in the annealed Ge layer, which explains the well-known shift in XRD peak position. The improvement in material quality by using a post-epi anneal is also reflected in the carrier lifetime as extracted from room-temperature photoluminescence measurements. The carrier lifetime increases from <0.2 ns (as-grown layers) to 3.3 ns and 3.6 ns for Ge on porous Si and bulk Si, respectively. The TDD, as extracted from ECCI measurements, was identical for both parts of the Si wafer (2-4e7 cm-2) and close to the values expected from literature. The material properties listed above are not affected by the thickness of the closed Si layer in-between the Ge and the porous Si.In conclusion, we developed a fabrication scheme for strain-relaxed Ge grown on SoN (or on macroporous Si) starting from conventional Si substrates. The material properties of the virtual Ge substrate are identical to those obtained for Ge grown on bulk Si. The virtual substrate serves as starting material for layer transfer and 3D device stacking technologies. The fabrication scheme can be extended to (defect free) bulk Ge for which the fabrication of Ge on nothing followed by layer transfer has been demonstrated [3].

Low temperature epitaxial growth of GaP on Si by atomic-layer deposition with plasma activation

An approach for epitaxial growth of GaP layers on Si substrates at low temperature (380 °C) by plasma-enhanced atomic layer deposition (PEALD) is explored. A significant improvement of the crystalline properties of the GaP layers is obtained using additional in-situ Ar plasma treatment. The epitaxial growth for the first 20–30 nm of GaP on Si is demonstrated from transmission electron microscopy. Moreover, the use of in-situ Ar plasma treatment during the PEALD process allows one to increase the growth rate per cycle from 0.9 ± 0.1 Å/cycle to 1.9 ± 0.1 Å/cycle and reduce the RMS roughness from 3.76 nm to 1.88 nm. The effect of Ar plasma treatment on the electronic properties of the GaP/Si interface is studied by deep level transient spectroscopy (DLTS). A defect level at (0.33 ± 0.03) eV below the conduction band is observed in the subsurface layer of Si for the GaP/Si structure grown under Ar plasma treatment. However, the defect response observed by DLTS vanishes after rapid thermal annealing at 500 ºC in nitrogen ambient.

Low-temperature epitaxial growth of high-quality GaON films on ZnO nanowires for superior photoelectrochemical water splitting

Gallium oxynitride (GaON) is an emerging material suitable as a key component to build efficient heterostructures for photoelectrochemical (PEC) water splitting. However, the great difficulty in controlled growth of GaON films limits their applications. This study developed a novel method for depositing highly uniform GaON films by a one-step co-deposition process via plasma-enhanced atomic layer deposition (ALD). Importantly, this material presents high-quality epitaxial growth behavior on ZnO nanowires (NWs) only at 200 °C to construct ZnO-GaON core-shell NWs with different shell thickness (5–60 nm). Benefiting from the precisely controlled ALD technique, thickness-dependent PEC performance and its mechanism were studied deeply. It was found the ZnO-GaON NWs with an optimum shell thickness (~40 nm) presented largest electric field enhancement and light-trapping ability, thus greatly improved the photocurrent from ~0.24 (pristine ZnO) to 2.25 mA/cm2 at 1.23 V versus reversible hydrogen electrode. Meanwhile, this structure presents an ultrahigh incident photon-to-current conversion efficiency of ~90% in the UV region. A comparative study assesses the ultrahigh carrier density (~1021 cm−3) and suitable bandgap of GaON relative to GaN and Ga2O3, revealing a higher photocurrent for the ZnO-GaON core-shell NWs. These encouraging results indicated that higher PEC performance is worthy expected upon optimization of the nitrogen and oxygen concentrations and by combining with narrow bandgap materials in further studies.

Low temperature epitaxial growth of Ge:B and Ge0.99Sn0.01:B source/drain for Ge pMOS devices: in-situ and conformal B-doping, selectivity towards oxide and nitride with no need for any post-epi activation treatment

We report on production compatible low temperature (≤320 °C) selective epitaxial growth schemes for boron doped Ge0.99Sn0.01 and Ge in source/drain areas of FinFET and gate-all-around (GAA) strained-Ge pMOS transistors. Active B concentrations are as high as 3.2 × 1020 cm−3 and 2.2 × 1020 cm−3 for Ge0.99Sn0.01 and Ge, respectively. The Ge:B growth is based on a cyclic deposition and etch approach using Cl2 as an etchant, while the Ge0.99Sn0.01:B growth is selective in nature. Low Ti/p+ Ge(Sn):B contact resistivities of 3.6 × 10−9 Ω cm2 (Ge0.99Sn0.01) and 5.5 × 10−9 Ω cm2 (Ge:B) have been obtained without any post-epi activation anneal. This work is the first demonstration of a selective, conformally doped Ge1−xSnx:B source/drain epi implemented on Ge FinFET device structure with fin widths down to 10 nm and on GAA devices (horizontal compressively strained-Ge nanowires).

Photorefractive effect of low-temperature-grown aluminum gallium arsenide

The ternary compound aluminum gallium arsenide is an important material that can be used in all-optical solid-state ultrafast diagnostic technology. The low-temperature-epitaxially-grown AlGaAs (LT-AlGaAs) not only has the characteristics of ultra-short carrier lifetime of low-temperature-grown gallium arsenide (LT-GaAs), but also possesses the advantage of adjustability of band gap, which will provide great flexibility for the design of ultra-fast diagnostic systems. We use low-temperature epitaxial growth technology to grow AlGaAs on a GaAs substrate. The low-temperature-grown AlGaAs can effectively absorb 400 nm pump light to generate excess carrier. Therefore, we use a femtosecond laser with a wavelength of 800 nm and a pulse width of 200 fs as a light source to generate 400-nm pump light after passing through the BBO crystal, and 800 nm light without frequency doubling as the probe light. Using such a light source, we build a pump probe experimental platform to test the LT-AlGaAs. We normalize the experimental results and deconvolute it with the normalized laser pulses to obtain the response function of the semiconductor to the pump light. Therefore, we know that the nonequilibrium carrier relaxation time is less than 300 fs, and the nonequilibrium carrier recombination time is 2.08 ps. Due to the special passivation process, the effect of surface recombination on the carrier decay process is greatly reduced. The As clusters introduced by low-temperature epitaxial growth form deep level defects are the main factor for accelerating carrier recombination. In order to understand the complex process of photogenerated nonequilibrium carriers in depth, we use the indirect recombination theory of single recombination center to calculate the carrier recombination process, and establish an LT-AlGaAs carrier evolution model. Thus we obtain the key physical parameter related to the recombination rate, which is the carrier trapping area. We also use a theoretical model of carrier-regulated refractive index to calculate the effect of carrier concentration on the amount of change in refractive index. Combining our AlGaAs carrier evolution model, we simulate the refractive index change process of LT-AlGaAs after being illuminated by pump light. The simulation results are in good agreement with the experimental results. The method can be used for the quantitative analysis of carrier evolution characteristics of semiconductor materials, and it can conduce to the optimization and improvement of ultra-fast response semiconductor materials.

Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

Low temperature (Ts/Tm &amp;lt; 0.1) epitaxial growth of HfN/MgO(001) via reactive HiPIMS with metal-ion synchronized substrate bias

Low-temperature epitaxial growth of refractory transition-metal nitride thin films by means of physical vapor deposition has been a recurring theme in advanced thin-film technology for several years. In the present study, 150-nm-thick epitaxial HfN layers are grown on MgO(001) by reactive high-power impulse magnetron sputtering (HiPIMS) with no external substrate heating. Maximum film-growth temperatures Ts due to plasma heating range from 70 to 150 °C, corresponding to Ts/Tm = 0.10–0.12 (in which Tm is the HfN melting point in K). During HiPIMS, gas and sputtered metal-ion fluxes incident at the growing film surface are separated in time due to strong gas rarefaction and the transition to a metal-ion-dominated plasma. In the present experiments, a negative bias of 100 V is applied to the substrate, either continuously during the entire deposition or synchronized with the metal-rich portion of the ion flux. Two different sputtering-gas mixtures, Ar/N2 and Kr/N2, are employed in order to probe effects associated with the noble-gas mass and ionization potential. The combination of x-ray diffraction, high-resolution reciprocal-lattice maps, and high-resolution cross-sectional transmission electron microscopy analyses establishes that all HfN films have a cube-on-cube orientational relationship with the substrate, i.e., [001]HfN||[001]MgO and (100)HfN||(100)MgO. Layers grown with a continuous substrate bias, in either Ar/N2 or Kr/N2, exhibit a relatively high mosaicity and a high concentration of trapped inert gas. In distinct contrast, layers grown in Kr/N2 with the substrate bias synchronized to the metal-ion-rich portion of HiPIMS pulses have much lower mosaicity, no measurable inert-gas incorporation, and a hardness of 25.7 GPa, in good agreement with the results for epitaxial HfN(001) layers grown at Ts = 650 °C (Ts/Tm = 0.26). The room-temperature film resistivity is 70 μΩ cm, which is 3.2–10 times lower than reported values for polycrystalline-HfN layers grown at Ts = 400 °C.

(Invited) Enabling Low Temperature and High Quality Epitaxial Films for Current and Future Nodes

Device scaling and new applications in nanoelectronics present increasing challenges to epitaxy. Reducing thermal budgets, compatibility with novel materials, increasing topology and higher device density require new strategies for both the epitaxial film growth itself and substrate preparation. In this talk we will review specific problems for enabling low temperature epitaxial growth and discuss the impact of non-volatile contaminants beyond oxygen on Si and SiGe epitaxy. We will compare multiple potential solutions and discuss their utility and limitations.

(Invited) Very Low Temperature Epitaxy of Group-IV Semiconductors for Use in FinFET, Stacked Nanowires and Monolithic 3D Integration

As CMOS scaling proceeds with sub-10 nm nodes, new architectures and materials are implemented to continue increasing performances at constant footprint. Strained and stacked channels and 3D-integrated devices have for instance been introduced for this purpose. A common requirement for these new technologies is a strict limitation in thermal budgets to preserve the integrity of devices already present on the chips. We present our latest developments on low-temperature epitaxial growth processes, ranging from channel to source/drain applications for a variety of devices and describe options to address the upcoming challenges.

Heterostructure modeling considerations for Ge-on-Si waveguide photodetectors

The computer-aided design and optimization of Ge-on-Si pin waveguide photodetectors is usually performed by a multiphysics analysis, where carrier transport is described with the drift-diffusion model. This paper addresses the shortcomings of this approach when applied to the study of the n-on-p detector configuration, ascribes them to the overly simplified model of the Si/Ge heterojunction, and proposes an enhanced description of the interfacial region. Starting from technological considerations, a thin buffer layer is introduced between Si and Ge, with a graded composition profile that mimics the initial low-temperature epitaxial growth process and mitigates the sharp discontinuity of the abrupt Si/Ge heterojunction in the band diagram. The benefits of this more realistic model on the determination of the electrooptic response are demonstrated and discussed.

Low-temperature surface preparation and epitaxial growth of ZnS and Cu2ZnSnS4 on ZnS(1 1 0) and GaP(1 0 0)

We give a summary of the low-temperature preparation methods of ZnS(110) and GaP(100) crystals for epitaxial growth of ZnS and Cu2ZnSnS4 (CZTS) via molecular beam epitaxy. Substrates were prepared for epitaxial growth by means of room-temperature aqueous surface treatments and subsequent ultra-high vacuum transfer to the deposition system. Epitaxial growth of ZnS was successful at 500K on both ZnS(110) and GaP(100) as only single domains were observed with electron backscatter diffraction; furthermore, transmission electron microscopy measurements confirmed an epitaxial interface. Epitaxial growth of CZTS was successful on ZnS at 700K. However, epitaxial growth was not possible on GaP at 700K due to GaxSy formation, which significantly degraded the quality of the GaP crystal surface. Although CZTS was grown epitaxially on ZnS, growth of multiple crystallographic domains remains a problem that could inherently limit the viability of epitaxial CZTS for model system studies.

The role of composition and microstructure in Ni–W silicide formation and low temperature epitaxial NiSi2 growth by premixing Si

We report on an extensive and detailed study of the silicide reaction of Ni–W alloys on Si(1 0 0). The solid phase reaction when studied over the full composition range reveals the substantial impact of composition and microstructure on the silicide reaction properties, such as the phase formation sequence and formation temperatures. It was found that the microstructure of the as-deposited film depends crucially on the alloy composition, being polycrystalline below 45 at.% W and amorphous above 45 at.% W. The microstructure affects the elemental mobility substantially, resulting in a drastic increase in the silicide reaction temperature in the case of an amorphous thin film. To further investigate the effect of elemental mobility, Si was premixed in the as-deposited alloy, thereby excluding the need for long-range diffusion. As a result, the silicide reaction temperatures were lowered. However, what was more striking was the observation of a bilayer structure for epitaxial NiSi2 in contact with the Si substrate and a W-rich layer residing at the outermost layer at a temperature of only 300 °C. The results stress the importance of the composition and crystalline nature of the as-deposited film, with these being decisive for the reaction sequence.