Low-temperature AlN Interlayers Research Articles

Relation of V/III ratio of AlN interlayer with the polarity of nitride

Abstract N-polar GaN film was obtained by using a high-temperature AlN buffer layer. It was found that the polarity could be inverted by a thin low-temperature AlN interlayer with the same V/III ratio as that of the high-temperature AlN layer. Continuing to increase the V/III ratio of the low-temperature AlN interlayer, the Ga-polarity of GaN film was inverted to N-polarity again but the crystal quality and surface roughness of GaN film greatly deteriorated. Finally, we analyzed the chemical environment of the AlN layer by x-ray photoelectron spectroscopy (XPS), which provides a new direction for the control of GaN polarity.

Role of low temperature Al(Ga)N interlayers on the polarity and quality control of GaN epitaxy

Polarity control is essential for lateral polarity heterostructures. N-polar GaN films were directly grown on high temperature AlN buffer layer. A thin low temperature AlN interlayer could invert the polarity of subsequent GaN layer to Ga-polarity but a low temperature GaN interlayer with the same condition could not do it rather deteriorate the quality of GaN film. In addition, a relationship between the yellow luminescence band and the surface roughness was discovered. The blue luminescence band was found only on the inverted Ga-polar GaN film and was connected to screw dislocation density.

Growth evolution of N-polar indium-rich InAlN layer on c-sapphire via strain relaxation by ultrathin AlON interlayer

InAlN as a functional inorganic material is a promising alternative to the commonly used InGaN in tunnel diodes and optoelectronic devices, due to its tunable wider range of energy bandgap (0.65–6.2 eV), thus empowering utilization of the whole solar spectrum. Moreover, high electron drift velocity and carrier concentration are considered as the most desirable prerequisite of indium-rich InAlN. N-polar indium-rich InAlN could be more beneficial due to the reverse direction of the polarization compared to Ga-polar. However, unanswered questions persist concerning growth evolution of N-polar indium-rich InAlN grown by organometallic chemical vapor deposition (OMCVD). In this study, energy dispersive X-ray spectroscopy (EDX) and high-angle annular dark-field (HAADF) imaging are used to characterize N-polar In0.60Al0.40N layer at nanometer scale in order to determine the evolution of the layer on (0001) sapphire substrate. Long nitridation of sapphire substrate leading to the formation of ~2 nm AlON ultrathin interlayer, which relaxes strain at the InAlN/sapphire interface with assistance of a low-temperature AlN interlayer is observed. EDX analysis confirms that after strain relaxation of InAlN layer, the indium-incorporation has only a weak dependence on the polarity of the layer. The incorporation of indium at preferential sites is also discussed at length.

MOVPE growth conditions optimization for AlGaN/GaN/Si heterostructures with SiN and LT-AlN interlayers designed for HEMT applications

In this work we present the influence of in situ deposited non-continous SiN layer and the chemical precursors III/V mole ratio change during GaN buffer growth for AlGaN/GaN/Si(111) heterostructures with low temperature AlN interlayer on their crystalline quality and electrical mobility of two dimensional electron gas (2DEG). We show, that application of SiN layer resulted in a decrease of (0002) full width at half maximum of diffraction peak below 400 arcsec and build-in stress in 2 µm thick heterostructures below 200 MPa without any relaxation visible on the surface. In optimized AlGaN/GaN heterostructures, by altering V/III mole ratio during growth of GaN subbuffer, the maximum 2DEG mobility of 2057 cm2 V−1 s−1, measured by impedance spectroscopy method, was obtained.

The preparation of different pairs near-ultraviolet AlGaN/GaN DBRs with AlN interlayer

In this paper, near-ultraviolet AlGaN/GaN distributed Bragg reflectors (DBRs) were prepared on GaN/sapphire templates by metal organic chemical vapor deposition. A single low-temperature AlN interlayer was adopted to prevent the formation of cracks in DBRs. Moreover, different pairs of DBRs with AlN interlayer were grown to investigate the stress distribution through the epilayer, the surface morphology evolution and the variation of reflectivity spectra. The in-situ stress monitoring shows a compressive-to-tensile stress transition with the increase of DBRs pairs. The optical microscope and atomic force microscope images show that the AlN interlayer induces the appearance of trenches on the surface of DBRs and the trenches gradually coalesce when DBRs grow. Meanwhile, the experimental reflectivity spectra get closer to the simulated results. Finally, we obtain a smooth-surface 25-pair Al.32Ga.68N/GaN DBRs with a reflectance of 94% at 390 nm and a 16 nm stopband bandwidth. The preparation of high-quality DBRs lays the foundation for the future development of high efficiency resonant cavity UV LEDs.

A low-temperature AlN interlayer to improve the quality of GaN epitaxial films grown on Si substrates

The quality of GaN epitaxial films on Si substrates is significantly improved by employing a low-temperature AlN interlayer. The relationship between the AlN interlayer growth temperature and the quality of GaN epitaxial films is systematically investigated. As the AlN interlayer growth temperature increases from 700 to 1000 °C, the crystalline quality of the GaN epitaxial films is firstly improved and then deteriorated. The GaN epitaxial film with the AlN interlayer grown at 800 °C shows the best crystalline quality, which is characterized by X-ray rocking curves with minimum full-width at half-maximum values of 370 and 452 arcsec for GaN (0002) and GaN (10–12), respectively. Further investigation reveals the fact that the low growth temperature of the AlN interlayer weakens the diffusion of Ga atoms from the AlGaN buffer layer into the AlN interlayer, thereby maintaining the lattice mismatch between the AlN interlayer and the GaN layer. The lattice mismatch facilitates the growth of 3-dimensional GaN which reduces the dislocation density effectively. This work provides a significant insight into the growth mechanism of GaN epitaxial films on Si substrates, which is critical for the fabrication of GaN-based devices on Si substrates.

Stress control by micropits density variation in strained AlGaN/GaN/SiN/AlN/Si(111) heterostructures

AlGaN/GaN heterostructures were deposited on Si utilizing in‐situ SiN masking layer as a mean to decrease stress present in the final heterostructures. Structures were grown under different V/III ratio using metalorganic vapour phase epitaxy (MOVPE). Additional approach was applied to obtain crack‐free heterostructures which was deposition of 15 nm low temperature AlN interlayer. Each of the heterostructure contained GaN layer of 2.4 μm total thickness. In‐situ SiN masking layer were obtained via introduction of SiH4 precursor into reactor under high temperature growth conditions for 100 s. In that manner, few monolayers of SixNx masking layer were deposited, which due to the partial coverage of AlN, played role of a mask leading to initial 3D growth mode enhancing longer coalescence of GaN buffer layer. To study surface morphology AFM images were observed. Three methods were used in order to obtain basal plane stress present in multilayer structures ‐ MicroRaman spectroscopy, XRD studies and optical profilometry. It was found that varying V/III precursors ratio during GaN layer growth characteristic for structures with the SiN mask approach formation of triangular micropits can be minimized. Outcomes for three different methods turned out to be coherent. It was found that certain amount of micropits on the surface can be advantageous lowering stress introduced during cooling after process to the AlGaN/GaN/SiN/AlN/Si(111) structure.

Optimization of AlGaN/GaN/Si(111) buffer growth conditions for nitride based HEMTs on silicon substrates

In this work we present results regarding growth of AlGaN/GaN/Si(111) HEMTs for integration of high frequency microelectronics with a silicon platform. GaN buffers with thicknesses above 1μm were grown using one or two low temperature LT-AlN interlayers. The impact of the number of LT-AlN interlayers as well as the influence of the V/III ratio during growth of the GaN buffer, on the surface morphology and electrical parameters of AlGaN/AlN/GaN/Si(111) heterostructures were studied.Obtained results show that application of low temperature AlN interlayers during growth of GaN on Si(111) is a valuable method of stress reduction in the deposited GaN layer and thus extends its critical thickness. However, deposition of a LT-AlN layer leads to a surface roughness and a decrease of GaN buffer resistivity. Growth of the GaN buffer with high V/III ratio enhances the buffer resistivity, 2DEG mobility and sheet carrier concentration. Optimized AlGaN/AlN/GaN/Si(111) heterostructure has similar mobility and sheet carrier concentration as a reference AlGaN/AlN/GaN heterostructure grown on sapphire.

Effects of lift-off and strain relaxation on optical properties of InGaN/GaN blue LED grown on 150 mm diameter Si (111) substrate

We report on the effect of strain relaxations induced by lift-off in an InGaN/GaN multiple quantum wells (MQWs) blue light-emitting diode (LED) structure grown by metal-organic chemical vapor deposition (MOCVD) on a 150-mm diameter Si (111) substrate. To manage the lattice strain and, meanwhile, filter the threading dislocations, an AlN nucleation layer followed by a fourfold-step-graded AlGaN buffer together with multiple low-temperature AlN interlayers hasbeen employed, which results in a crack-free growth of 4.9-µm GaN on Si (111) in the studied LED structure. High-resolution x-ray diffraction (HRXRD) and micro-Raman spectroscopy reveal that MQWs are coherently grown on the GaN layer while the GaN layer is tensile strained on the Si (111) substrate. Lift-off by wet-chemical etching results in phonon softening of both the top-layer GaN and the InGaN within the QWs; meanwhile, a red-shift of ~11meV in the photoluminescence (PL) from the MQWs accompanied by a significant decrease (>4.9 times) in the PL-peak decay time is observed at room temperature. These observations are discussed and associated with the lift-off induced strain relaxations, which change the wafer curvature that in turn results in redistribution of in-plane stresses along the growth direction in the GaN-on-Si LED structure.

Void formation during GaN MOVPE on Si (111) employing low temperature AlN interlayers

AbstractDuring the growth of GaN on Si (111), voids were found in GaN layers in between AlN interlayers. Void formation mechanism is the decomposition of GaN in H2. Void formation process is carefully studied. It is clarified that voids are formed during the period between the growth of two neighbouring GaN layers, after the growth of AlN interlayer between them. There are some openings in AlN interlayers and they act as the pass for H2 to react with GaN. NH3 partial pressure, temperature, etching time, and conditions such as thickness of AlN interlayers can be utilized to tune the volume, size and shape of the voids. (© 2014 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Investigations of leakage current properties in semi-insulating GaN grown on Si(1 1 1) substrate with low-temperature AlN interlayers

In this work, the leakage current properties of semi-insulating GaN (SI-GaN) grown on Si(1 1 1) substrate with a low-temperature (LT) AlN interlayer were studied. Two terminal lateral current–voltage measurements revealed an early conduction phenomenon via buffer layers with an LT-AlN interlayer, in which both p- and n-type conduction phenomena were observed from Hall-effect measurement during temperature changing. It is suggested that the p-type conduction existed in the Si substrate due to the diffusion of Al atoms into the Si substrate during the epitaxial growth. The origin of n-type conduction was two-dimensional electron gas (2DEG) in the LT-AlN/GaN interface, which acted as a conduction channel in SI-GaN. Furthermore, the vertical leakage current measurement and the space charge limited current model were used to analyse the impact of the 2DEG conduction channel on the leakage current properties. It is revealed that leakage current properties are very sensitive to the thickness of the GaN layer above the LT-AlN interlayer (Top-GaN). Increasing the thickness of Top-GaN becomes an effective way to suppress leakage current. Therefore, both strain engineering and leakage current properties are essential factors to be considered in the selection of strain compensation interlayer in the growth of SI-GaN on Si substrate for power switching applications.

Thickness optimization of GaN layers by in‐situ observation of GaN MOVPE on Si (111)

AbstractFor MOVPE grown GaN on Si (111) employing low temperature AlN interlayers, in terms of compressive stress introduction to avoid cracking, factors determining the proper thickness of GaN layers were investigated, with the help of in‐situ observation of multi‐wavelength reflectance patterns and curvature transition. For the 1st GaN layer, the stress behavior of it depends on the growth conditions of AlN buffer layer. For the case on an improper AlN buffer layer, GaN takes tensile stress easily and thus its thickness should be limited to reduce the amount of tensile stress. On the contrary, on the optimized AlN buffer layer, the GaN on it was compressively strained and its thickness can be large to introduce more compressive stress. For GaN layers in between AlN interlayers, the thickness should be limited to be less than the critical thickness in which the layer starts to relax. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

The management of stress in MOCVD-grown InGaN/GaN LED multilayer structures on Si(1 1 1) substrates

The tensile stress in light-emitting diode (LED)-on-Si(1 1 1) multilayer structures must be reduced so that it does not compromise the multiple quantum well emission wavelength uniformity and structural stability. In this paper it is shown for non-optimized LED structures grown on Si(1 1 1) substrates that both emission wavelength uniformity and structural stability can be achieved within the same growth process. In order to gain a deeper understanding of the stress distribution within such a structure, cross-sectional Raman and photo-luminescence spectroscopy techniques were developed. It is observed that for a Si:GaN layer grown on a low-temperature (LT) AlN intermediate layer there is a decrease in compressive stress with increasing Si:GaN layer thickness during MOCVD growth which leads to a high level of tensile stress in the upper part of the layer. This may lead to the development of cracks during cooling to room temperature. Such a phenomenon may be associated with annihilation of defects such as dislocations. Therefore, a reduction of dislocation intensity should take place at the early stage of GaN growth on an AlN or AlGaN layer in order to reduce a build up of tensile stress with thickness. Furthermore, it is also shown that a prolonged three dimensional GaN island growth on a LT AlN interlayer for the reduction of dislocations may result in a reduction in the compressive stress in the resulting GaN layer.

Electrical properties of MOCVD-grown GaN on Si (111) substrates with low-temperature AlN interlayers

The electrical properties of the structure of GaN grown on an Si (111) substrate with low-temperature (LT) AlN interlayers by metal—organic chemical-vapour deposition are investigated. An abnormal P-type conduction is observed in our GaN-on-Si structure by Hall effect measurement, which is mainly due to the Al atom diffusing into the Si substrate and acting as an acceptor dopant. Meanwhile, a constant n-type conduction channel is observed in LT-AlN, which causes a conduction-type conversion at low temperature (50 K) and may further influence the electrical behavior of this structure.

Growth and stacking fault reduction in semi‐polar GaN films on planar Si(112) and Si(113)

AbstractWe report on metal organic vapor phase epitaxy of semi‐polar growth of nearly (1$ \bar 1 $06) oriented GaN films on Si(112) and (1$ \bar 1 $05) and (1$ \bar 1 $04) GaN on Si(113). We analyze the GaN crystallites by field emission‐scanning electron microscopy (FE‐SEM), scanning transmission electron microscopy (STEM), photoluminescence (PL), and cathodoluminescence (CL). A correlation between optical properties and microstructure is presented. Our studies reveal a significant reduction of basal plane stacking faults (BSFs) in semi‐polar GaN grown on planar Si(112) by applying a low temperature (LT) AlN interlayer. We find that the insertion of the LT‐AlN interlayer can eliminate the stacking faults in the upper GaN layer, when the LT‐AlN interlayer is inserted on a smooth GaN buffer. The LT‐AlN interlayer results in lattice relaxation due to misfit dislocation formation at the GaN/LT–AlN interface. In comparison, GaN grown on Si(113) with same growth conditions and a rough GaN surface does not show any BSF reduction while it is reduced for a smooth GaN layer (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Different strain relief behaviors in Al0.35Ga0.65N/GaN multiple quantum wells on GaN/Sapphire templates with AlN/GaN supperlattices and low-temperature AlN interlayers

Strain relief behaviors in Al0.35Ga0.65N/GaN multiple quantum wells (MQWs) grown on GaN/sapphire templates with either AlN/GaN supperlattices (SLs) or low-temperature AlN (LT-AlN) interlayers (ILs) between the MQWs and templates have been investigated. These two IL techniques can both effectively relieve the tensile strain in the MQWs, leading to crack-free surfaces and high crystalline quality. Further analysis shows that there are two distinct strain relief channels. In the case of adopting AlN/GaN SLs IL, microcracks and misfit dislocations account for strain relief in the MQWs. Microcracks are first generated in the IL, followed by activating formation of misfit dislocations. Then, the microcracks are immediately filled up by the subsequent epilayers. Contrastively, strain relief by using LT-AlN IL is mainly through the self relaxation process of the MQWs by surface roughening and strain compensation effect of LT-AlN IL.

Influence of V/III Ratio of Low Temperature Grown AlN Interlayer on the Growth of GaN on Si Substrate

In this work, the influence of the V/III ratios of the low temperature (LT) AlN interlayer on GaN grown on Si<111> substrate have been investigated. It was found that V/III ratio of LT-AlN interlayer is another important growth parameter, which the crystalline quality of GaN was strongly dependent on. By optimizing the V/III ratio of LT-AlN, the high quality crack-free GaN epilayer with lower dislocation density on Si substrate have been obtained. We attribute it to the different LT-AlN surface morphology originated from optimizing the V/III ratio. Different V/III ratios could result in different GaN growth rates in vertical and lateral direction, which could effectively prevent the threading dislocation from penetrating through the LT-AlN interlayer.

Influence of V/III Ratio of Low Temperature Grown AlN Interlayer on the Growth of GaN on Si&lt;111&gt; Substrate

In this work, the influence of the V/III ratios of the low temperature (LT) AlN interlayer on GaN grown on Si<111> substrate have been investigated. It was found that V/III ratio of LT-AlN interlayer is another important growth parameter, which the crystalline quality of GaN was strongly dependent on. By optimizing the V/III ratio of LT-AlN, the high quality crack-free GaN epilayer with lower dislocation density on Si substrate have been obtained. We attribute it to the different LT-AlN surface morphology originated from optimizing the V/III ratio. Different V/III ratios could result in different GaN growth rates in vertical and lateral direction, which could effectively prevent the threading dislocation from penetrating through the LT-AlN interlayer.

Eliminating stacking faults in semi-polar GaN by AlN interlayers

We report on the elimination of stacking faults by the insertion of low-temperature AlN interlayers in nearly (1016) and (11¯04) oriented semi-polar GaN grown by metalorganic vapor phase epitaxy on Si(112) and Si(113), respectively. The elimination of these defects is visualized by cathodoluminescence (CL) as well as scanning transmission electron microscopy (STEM) and STEM-CL. A possible annihilation mechanism is discussed which leads to the conclusion that the elimination mechanism is most likely valid for all layers with (11¯01) surfaces, enabling heteroepitaxial semi- and non-polar GaN free from stacking faults.

Crack-free III-nitride structures (&gt; 3.5 μm) on silicon

ABSTRACTIII-nitride structures on Si are of great technological importance due to the availability of large area, epi ready Si substrates and the ability to heterointegrate with mature silicon micro and nanoelectronics. High voltage, high power density, and high frequency attributes of GaN make the III-N on Si platform the most promising technology for next-generation power devices. However, the large lattice and thermal mismatch between GaN and Si (111) introduces a large density of dislocations and cracks in the epilayer. Cracking occurs along three equivalent {1−100} planes which limits the useable device area. Hence, efforts to obtain crack-free GaN on Si have been put forth with the most commonly reported technique being the insertion of low temperature (LT) AlN interlayers. However, these layers tend to further degrade the quality of the devices due to the poor quality of films grown at a lower temperature using metal organic chemical vapor deposition (MOCVD). Our substrate engineering technique shows a considerable improvement in the quality of 2 μm thick GaN on Si (111), with a simultaneous decrease in dislocations and cracks. Dislocation reduction by an order of magnitude and crack separation of &gt; 1 mm has been achieved. Here we combine our method with step-graded AlGaN layers and LT AlN interlayers to obtain crack-free structures greater than 3.5 μm on 2” Si (111) substrates. A comparison of these film stacks before and after substrate engineering is done using atomic force microscopy (AFM) and optical microscopy. High electron mobility transistor (HEMT) devices developed on a systematic set of samples are tested to understand the effects of our technique in combination with crack reduction techniques. Although there is degradation in the quality upon the insertion of LT AlN interlayers, this degradation is less prominent in the stack grown on the engineered substrates. Also, this methodology enables a crack-free surface with the capability of growing thicker layers.