Low-swing Signaling Research Articles

Technology scaling impact on VLSI interconnect and low swing signaling technique

Technology scaling impact on VLSI interconnect and low swing signaling technique

Efficient Error-Resilient Bus Coding Method Using Bit-Basis Orthogonal Integrative Multiplexing

Interconnection technologies must consider reliability problems in dense on-chip networks, where a large number of routing elements constitute the global tracks for bus transactions through high-speed and low-swing signals. As the density of device integration continues to evolve and even employ multilevel states, technologies must effectively cope with dynamic errors to maintain system reliability. The primary objective of this study is to develop an atomic hardware multiplexer to decrease signal errors that can be applied to fault-tolerant routing resources in the digital domain. We propose a new bus coding method named bit-basis code division multiplexing (BCDM) and multidimensional expansions to integrate multi-source digital signals. The concurrent multiplexing techniques offered here can enhance the random noise immunity of the existing differential and duplicating bus transactions. Additionally, we demonstrate that simple parity and receiving integration improve the applicability of the BCDM. In numerical simulations, the proposed BCDM variants exhibited lower error rates and fewer transmission costs than existing methods. In a mesh-type spiking neural network, these methods can be used to multiplex the individual router taps and provide immunity from random noise. In a 32-nm CMOS technology library, the gate-count overhead of the multiplexing operators was only 3.6% of the baseline design.

A 3-D IC for Mitigating Energy of Memory Accessing and Data Movement in Accelerator- Based Streaming Architectures

This paper presents a 3-D integrated circuit (3-D IC) for heterogeneous domain-specific streaming architectures. In such architectures, an array of fine-grained accelerators is provided for executing kernels, and applications are mapped via configuration of the accelerators into a desired computation pipeline. The two-layer 3-D IC addresses architectures for different application domains, through a generic routing-and-memory (RM) layer and a separate compute-accelerator (CA) layer, which could ultimately be selected at assembly time for different application domains. The RM layer provides a configurable routing network, as well as memory for pipeline buffering and computation scratch pad. The routing network is based on a 2-D mesh with low-swing signaling. The memory is organized as 32 fine-grained (1-kB) SRAM tiles for increased interface parallelism, reduced access energy, and modularity, to interface with different accelerators in the CA layer. Memory-driver and sensing circuits are reused by the low-swing routing network, both for repeaters and to directly load pipeline data into accelerator input buffers. For the prototype, the CA layer is implemented as an array of multiplexers, providing off-chip interfacing to any memory title, thereby enabling different accelerators to be emulated by an off-chip field-programmable gate array (FPGA). The 3-D interconnection is achieved by 8- $\mu \text{m}$ -pitch face-to-face (F2F) vias and wafer-level assembly. For the $2.47\times 3.38$ mm2 two-layer die, implemented in 130-nm CMOS, the total peak memory bandwidth is 9.2 GB/s/mm2. A compute pipeline for computational photography is demonstrated, with the total energy of the accelerators reduced by over 2 $\times $ , by exploiting parallelism enabled by interfaces to fine-grained RM-layer memory.

A variation tolerant current mode low swing signaling approach for gigascale on-chip interface circuit

Enhanced functionality per unit area is the gradually increasing demand of current manufacturing market and that desire has been fulfilled by aggressive down scaling of technology, which has adversely influenced the delay of global interconnect thereby affecting the performance of high speed design. As the time needed to charge or discharge the output node of a circuit is directly proportional to the peak-to-peak swing of the driven signal, there remains an inherent speed advantage in low swing signaling, which is considered to be one of the most suitable options to eliminate signal integrity issues in multi-gbps chip-to-chip communication. This article unveils a detailed report on the shortcomings of existing low swing signaling schemes, where no work is witnessed to generate a certain low voltage swing across any reference voltage ranging from ‘Logic 0’ to ‘Logic 1’ of the input signal. To address the same, we have come up with a novel methodology consisting of two different current sources (one at driver and the other at receiver) made of NMOS. In this case, the said reference voltage corresponds to the threshold of the receiver chip, which has to be identified at first. The simulation of proposed low swing signaling scheme is carried out using 65 nm, 45 nm and 22 nm CMOS technology to examine the performance metrics at 1.1 V supply while switching at 2 GHz. This approach does provide extensive delay and energy or PDP savings to outsmart the existing works.

Power Efficient Clock Distribuition for Switched Capacitor DC-DC Converters

<p>In various VLSI based digital systems, on-chip interconnects have become the system bottleneck in state-of-the-art chips, limiting the performance of high-speed clock distributions and data communication devices in terms of propagation delay and power consumption. Increasing power requirements and power distribution to multi-core architectures is also posing a challenge to power distribution networks in the integrated circuits. Clock distribution networks for the switched capacitor converters becomes a non-trivial task and the increased interconnect lengths cause clock degradation and power dissipation. Therefore, this paper introduce low swing signaling schemes to decrease delay and power consumption. A comparative study presented of low voltage signaling schemes in terms of delay, power consumption and power delay product. Here, we have presented a power efficient signaling topology for driving the clocks to higher interconnect lengths.</p>

A Tunable Swing-Reduced Driver in 0.13-μm MTCMOS Technology

With the increase in demand for high-speed and low-power integrated circuits as technology scales down, low-swing signaling circuit techniques are critical for providing high-speed low-power communications. However, existing low-swing circuits comprise complex designs, power issues (static and dynamic), output voltage swing restrictions or nonadjustable voltage swing levels, leading to lower operation speeds and even larger area footprints. In this paper, a tunable swing-reduced driver (SRD) circuit featuring the mentioned design challenges is presented. The SRD enables low-swing signals with fully controllable output voltage swing that is useful to reduce the power dissipation and delay in the signaling paths. Implemented in UMC 0.13-[Formula: see text][Formula: see text]m multi-threshold CMOS process, the SRD achieves 26 ps propagation delay at 200[Formula: see text]mV output swing for a pulse signal input at 1[Formula: see text]GHz. Post-layout simulations of the proposed SRD and a DAC application circuit, incorporating the SRD, operating at 1[Formula: see text]GHz, validate the design.

Delay Analysis and Design Optimization for Low-Swing RC-Limited Global Interconnects

On-chip global interconnects are becoming speed and power bottlenecks in state-of-the-art chips. Low-swing signaling is used to improve delay performance and reduce power consumption. This paper first performs a delay analysis for different low-swing circuits based on the Asymptotic Waveform Evaluation (AWE). In addition, new delay metrics are presented and analyzed. The new delay metrics demonstrate that optimal designs can be obtained in low-swing signaling. To verify our analysis, a simulation environment is established. The simulation results indicate that the optimal designs can increase the 3[Formula: see text]dB bandwidth of a wire by more than 40% in resistively driven or capacitively driven 10[Formula: see text]mm global links. Thus, these optimal design methods can effectively improve the bandwidth of global wires.

Low Energy yet Reliable Data Communication Scheme for Network-on-Chip

In this paper, a low energy yet reliable communication scheme for network-on-chip is suggested. To reduce the communication energy consumption, we invoke low-swing signals for transmitting data, as well as data encoding techniques, for minimizing both self and coupling switching capacitance activity factors. To maintain the communication reliability of communication at low-voltage swing, an error control coding (ECC) technique is exploited. The decision about end-to-end or hop-to-hop ECC schemes and the proper number of detectable errors are determined through high-level mathematical analysis on the energy and reliability characteristics of the techniques. Based on the analysis, the extended single error correction double-error detecting end-to-end coding technique with three bits of error detection is used in the network layer. For minimization of the self and coupling switching capacitance activity factors, the odd, even, full invert scheme is employed in the data link layer. This coding has an inherent error detection probability for the flits, which is exploited in the suggested technique. The efficiency of the scheme is studied by using both synthetic and real traffic scenarios. The study reveals savings of up to 43% and 58%, for power dissipation and energy consumption, respectively, without any significant performance degradation and overhead in the network interface.

13-Gbps 저스윙 저전력 니어-그라운드 시그널링 트랜시버

13-Gbps 저스윙 저전력 니어-그라운드 시그널링 트랜시버

CCS: A low-power capacitively charge-sharing transmitter for NoC links

In this letter, a capacitively charge-sharing transmitter (CCS) is proposed as a novel design to replace the traditional differential capacitive pre-emphasis transmitter (CPE), for the purpose of reducing the dynamic power consumption by half. The CCS functions as a transmitter for mesh NoC links to achieve high-speed and low-power transmission. CCS generates a pair of differential low-swing signals at a time through charge-sharing. Its capacitively driven mode enables high-speed transmission and provides pre-emphasis to extend the bandwidth. Simulation shows that CCS can achieve 9Gb/s data rate over 2mm twisted differential interconnects with only 56.4fJ/b power consumption. With a clockless hysteresis receiver, the transceiver for NoC links enables a data rate of 7Gb/s with at least 70% eye-opening while consumes only 90.8fJ/b.

The Performance and Analysis of an Efficient Model of DC to DC Converter for on Chip Circuitry using a Less Number of Power Devices

This paper presents an efficient DC to DC converter for on chip circuitry which gives high-energy conversion quality using CMOS Driver-Receiver Pair for Low-Swing Signaling. The efficiency has increased due to the use of power FETs, which are able to switch at high frequency more efficiently than power bipolar transistors, which incur more switching losses and require a more complicated drive circuit. The proposed schemes perform better than the other schemes in terms of power consumption, delay, and energy delay product. Moreover, the proposed scheme requires no reference voltages, and multiple threshold voltage processes. In addition the other key advantages of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This proposed work also takes care of the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link

This paper presents the design of a high-speed ultra low power SRAM memory. Divided bit lines improve dynamic cell stability while at the same time decreasing active energy consumption. To limit unnecessary activity, word lines are divided on a word-by-word basis. Local write sense amplifiers make it possible to use low swing signaling on the global bit lines. To control this architecture, a distributed decoder is used. The use of dual swing data links on the global bit lines limits the impact of local write sense amplifier offset on the overall energy consumption. Using high threshold transistors in the memory cells reduces static power consumption and improves the cell's read stability. A partly dynamic decoder structure increases memory speed at a very low energy cost. The timing of this memory is made configurable to be able to cope with PVT variations without increasing design margins. The designed 256 kbit memory was fabricated in a 65 nm triple-V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> process. It operates up to a speed of 850 MHz while only consuming 4.3 pJ/access for a word length of 32 bit. Standby leakage power is 25.2 W. This memory clearly outperforms other state-of-the-art designs when targeting high-speed, low-leakage and low active energy applications.

Design and analysis of a low-swing driver scheme for long interconnects

Market forces are continually demanding devices with increased functionality/unit area; these demands have been satisfied through aggressive technology scaling which, unfortunately, has impacted adversely on the global interconnect delay subsequently reducing system performance. Line drivers have been used to mitigate the problems with delay; however, these have large power consumption. A solution to reducing the power dissipation of the drivers is to use lower supply voltages. However, by adopting a lower power supply voltage, the performance of the line drivers for global interconnects is impaired unless low-swing signalling techniques are implemented. The paper describes the design of a low-swing signalling scheme which consists of a low-swing driver, called the nLVSD driver which is an improved version of the MJ-driver [1] designed by Juan A. Montiel-Nelson and Jose C. Garcia. Subsequently, both low-swing driver schemes are analysed and compared focusing on their power consumption and performance characteristics, which are the main issues in present day IC design. A comparison between the two driver schemes showed that the nLVSD driver exhibited a 34% improvement regarding power consumption and a 28% improvement in delay when driving a 10mm length of interconnect. A comparison between the two schemes was also undertaken in the presence of ±3σ Process and Voltage (PV) variations. The analysis indicated that the nLVSD driver scheme was more robust than the MJ-driver with a 33% and 44% improvement with respect to power consumption and delay variations. In order to further improve the robustness of the nLVSD scheme against process variation, the scheme was further analysed to identify which process variables had the most impact on circuit delay and power consumption. For completeness the effects of process variation on interconnect delay and power consumption was also undertaken.

Low-Power, Resilient Interconnection with Orthogonal Latin Squares

A reliable, energy-efficient on-chip interconnection network employing low-swing signaling can be designed by incorporating error-correcting code. Orthogonal Latin Square Code (OLSC) can protect the interconnection against transient errors, while also lowering energy consumption. When applied to a 64-bit link using a 45-nm CMOS technology with low-swing signaling, OLSC provided up to 55% energy reduction, with only a small area overhead and no loss in reliability.

Variability compensation for full-swing against low-swing on-chip communication

Adaptive body bias (ABB) and adaptive supply voltage (ASV) are effective methods for post-silicon tuning to reduce variability on generic combinational circuits or microprocessor circuit sub-blocks. We focus in this work on global point-to-point interconnects, which are evolving into complex communication channels with drivers and receivers, in an attempt to mitigate the effects of reverse scaling and reduce power. The characterisation of the performance spread of these links and the exploration of effective and power-aware compensation techniques for them is becoming a key design issue. This work compares the effectiveness of ABB against ASV when put at work on two on-chip point-to-point link architectures: a traditional full-swing and a low-swing signalling scheme for low-power communication. This work provides guidelines for the post-silicon variability compensation of these communication channels, while considering realistic layout effects. In particular, the implications of cross-coupling capacitance on the effectiveness of variability compensation are analysed in this work.

Low-Swing Signaling on Monolithically Integrated Global Graphene Interconnects

In this paper, we characterize the performance of monolithically integrated graphene interconnects on a prototype 0.35-μm CMOS chip. The test chip implements an array of transmitter/receivers to analyze the end-to-end data communication on graphene wires. Large-area graphene sheets are first grown by chemical vapor deposition, which are then subsequently processed into narrow wires up to 1 mm in length. A low-swing signaling technique is applied, which results in a transmitter energy of 0.3-0.7 pJ/b·mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> and a total energy of 2.4-5.2 pJ/b·mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . Bit error rates below 2 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> are measured using a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 pseudorandom binary sequence. Minimum voltage swings of 100 mV at 1.5-V supply and 500 mV at 3.3-V supply have also been demonstrated. At present, the graphene wire is largely limited by its growth quality and high sheet resistance.

Fully Integrated Graphene and Carbon Nanotube Interconnects for Gigahertz High-Speed CMOS Electronics

Carbon-based nanomaterials such as metallic single-walled carbon nanotubes, multiwalled carbon nanotubes (MWCNTs), and graphene have been considered as some of the most promising candidates for future interconnect technology because of their high current-carrying capacity and conductivity in the nanoscale, and immunity to electromigration, which has been a great challenge for scaling down the traditional copper interconnects. Therefore, studies on the performance and optimization of carbon-based interconnects working in a realistic operational environment are needed in order to advance the technology beyond the exploratory discovery phase. In this paper, we present the first demonstration of graphene interconnects monolithically integrated with industry-standard complementary metal-oxide-semiconductor technology, as well as the first experimental results that compare the performance of high-speed on-chip graphene and MWCNT interconnects. The graphene interconnects operate up to 1.3-GHz frequency, which is a speed that is commensurate with the fastest high-speed processor chips today. A low-swing signaling technique has been applied to improve the speed of carbon interconnects up to 30%.

CMOS design and analysis of low-voltage signaling methodology for energy efficient on-chip interconnects

This paper provides a comparative study of the low-voltage signaling methodologies in terms of delay, energy dissipation, and energy delay product (energy×delay), and sensitivity technology process variations, and noise. We also present the design of two symmetric low-swing driver–receiver pairs for driving signals on the global interconnect lines. The key advantage of the proposed signaling schemes is that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. The proposed signaling schemes were implemented on 1.0V 0.13μm CMOS technology, for signal transmission along a wire-length of 10mm. When compared with other counterpart symmetric and asymmetric low-swing signaling schemes, the proposed schemes perform better in terms of delay, energy dissipation and energy×delay.

CMOS Driver-Receiver Pair for Low-Swing Signaling for Low Energy On-Chip Interconnects

This paper describes the design of symmetric low-swing driver-receiver pairs (mj-sib) and (mj-db) for driving signals on the global interconnect lines. The proposed signaling schemes were implemented on 1.0 V 0.13-mum CMOS technology, for signal transmission along a wire-length of 10 mm and the extra fan-out load of 2.5 pF (on the wire). The mj-sib and mj-db schemes reduce delay by up to 47% and 38% and energy-delay product by up to 34% and 49%, respectively, when compared with other counterpart symmetric and asymmetric low-swing signaling schemes. The other key advantages of the proposed signaling schemes are that they require only one power supply and threshold voltage, hence significantly reducing the design complexity. This paper also confirms the relative reliability benefits of the proposed signaling techniques through a signal-to-noise ratio (SNR) analysis.

Coding for reliable on-chip buses: a class of fundamental bounds and practical codes

A reliable high-speed bus employing low-swing signaling can be designed by encoding the bus to prevent crosstalk and provide error correction. Coding for on-chip buses requires additional bus wires and codec circuits. In this paper, fundamental bounds on the number of wires required to provide joint crosstalk avoidance and error correction using memoryless codes are presented. The authors propose a code construction that results in practical codec circuits with the number of wires being within 35% of the fundamental bounds. When applied to a 10-mm 32-bit bus in a 0.13-μm CMOS technology with low-swing signaling, one of the proposed codes provides 2.14× speedup and 27.5% energy savings at the cost of 2.1× area overhead, but without any loss in reliability.