Low Spur Research Articles

A Low Spur 5.9-GHz CMOS Frequency Synthesizer with Loop Sampling Filter for C-V2X Applications

In this paper, a very low spur 5.9-GHz integer-N frequency synthesizer designed for a Cellular Vehicle-to-Everything (C-V2X) receiver is presented. The PLL is referenced to a 10-MHz crystal oscillator and the design is implemented in a 65-nm CMOS process. The output of the synthesizer has differential quadrature topology and provides the local oscillator signal to a downconverter mixer of C-V2X receiver. Post-layout simulations show that the reference spurs are better than −88[Formula: see text]dBc through loop sampling technique which was implemented in a 11.8-GHz VCO design for the first time to the best of our knowledge. The best spur level without the loop sampling technique applied is limited to −55[Formula: see text]dBc. Using the loop sampling technique provides a spur reduction of 33[Formula: see text]dB which is a significant improvement at this frequency. Based on post-layout simulations, the design has a phase noise of −97/−99/−114[Formula: see text]dBc for 10[Formula: see text]kHz/100[Formula: see text]kHz/1[Formula: see text]MHz frequency offsets, respectively, which presents competitive numbers with the designs in the literature. The design has 1.2-V nominal supply voltage for the analog and digital blocks. The total power dissipation of the synthesizer core is 6[Formula: see text]mW from a 1.2-V supply while the output buffers driving a 100-fF load consumes 18[Formula: see text]mW.

A 0.3-to-1-GHz IoT Transmitter Employing Pseudo-Randomized Phase Switching Modulator and Single-Supply Class-G Harmonic Rejection PA

A wideband Internet of Things (IoT) transmitter (TX) employing open-loop binary frequency-shift keying (BFSK) modulator with a pseudo-randomized phase transition (PRPT) time and a single-supply Class-G harmonic rejection (HR) power amplifier (PA) is presented. The proposed open-loop phase switching modulator eliminates the data-rate limitation in a conventional phase-locked loop (PLL)-based closed-loop modulator, while the PRPT scheme increases the effective phase resolution with a better power efficiency than delta–sigma modulation (DSM)-based randomization. Thus, a low spur level below −40 dBc is achieved with only a 4-bit phase resolution. The Class-G HR PA, including a four-level supply voltage waveform generator, is proposed as a high-efficiency and low spurious PA architecture. The proposed HR PA presents the third- and fifth-harmonics cancellation over the 0.3-to-1-GHz band, while only a single supply is required for Class-G implementation of the HR PA. The proposed BFSK TX is implemented in a 55-nm CMOS process. Measured with a 0.3-to-1-GHz continuous-wave carrier, TX output power and PA drain efficiency are 2.7 ± 0.2 dB and 52% ± 3%, respectively, operating from a 0.9-V supply. The HRs of −31.4/−42.7 and −28.2/−42.4 dBc at the third/fifth harmonics are measured at the lowest (0.3 GHz) and the highest (1 GHz) carrier frequencies, respectively. With a data rate of 1 Mb/s, the measured FSK errors are 3.6% and 4.2% at both ends of the operating frequency.

Reference Oversampling PLL Achieving −256-dB FoM and −78-dBc Reference Spur

This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this article proposes an LC digitally controlled oscillator (DCO) for the proposed OSPLL to achieve a fast frequency update and fine frequency resolution, while its varactor switching timing is set optimally for low jitter using the proposed DCO tuning pulse timing control scheme. The proposed OSPLL was fabricated in a 28-nm CMOS process. The integrated rms jitter of the PLL was measured at 67.1 fs for an output frequency of 4 GHz. The in-band phase noise of the PLL was −129.2 and −132.5 dBc/Hz at 1- and 5-MHz offset frequencies. The measured reference spur of the PLL was −78.1 dBc. Total PLL power consumption was 5.2 mW, resulting in −256.3-dB PLL jitter-power FoM, while occupying 0.17-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

A Low Spur and Low Jitter Quadrature LO-Generator Using CML Inductive Peaking Technique for WLAN Transceiver

The demand for a local oscillator (LO) signal of high quality and integrity in local area network (WLAN) communication is growing with the increasing date rate. The LO signals for high data rate WLAN applications are desired to not only have proper shape waveforms and adequate voltage amplitude but also to achieve relatively stable and clean outputs with low phase noise and low spur. Fractional-N frequency planning is critical for a quadrature LO-generator, which is achieved by a single-sideband (SSB) mixer and multiple dividers since it can avoid the frequency pulling and alleviate the self-mixing and DC offset issues, while spur levels are easily increased due to harmonic mixing, imbalance, and leakage of the SSB mixer. This article proposes a simple and innovative quadrature LO-generator, which adopts a current-mode-logic (CML) inductive peaking (IP) circuit to improve phase noise and suppress spurious tones. Four types of LO delivery methods using IP circuits are proposed and compared. Among four methods, the CML-IP circuit presents the optimum performance for driving long wires of multi-mm length. Instead of previous digital spur cancellation, the CML-IP circuit achieves higher spur suppression, lower jitter, and a greater figure of merit (FoM). The quadrature LO-generator can be configured to either VCO mode or bypass mode supporting external VCO input. Implemented in 55 nm CMOS technology, the proposed quadrature LO-generator achieves −52.6 dBc spur suppression, −142 dBc/Hz phase noise at 1 MHz offset at the 4.8 GHz frequency, and −271 FoM. Furthermore, the quadrature LO-generator occupies an active area of 0.178 mm2 and consumes 23.86 mW.

Low excitation spur gears with variable tip diameter

One important source of noise in drive trains are transmissions. In numerous applications, it is necessary to use helical instead of spur gear stages due to increased noise requirements. Besides a superior excitation behaviour, helical gears also show additional disadvantageous effects (e.g. axial forces and tilting moments), which have to be taken into account in the design process. Thus, a low noise spur gear stage could simplify design and meet the requirements of modern mechanical drive trains. The authors explore the possibility of combining the low noise properties of helical gears with the advantageous mechanical properties of spur gears by using spur gears with variable tip diameter along the tooth width. This allows the adjustment of the total length of active lines of action at the beginning and end of contact and acts as a mesh stiffness modification. For this reason, several spur gear designs are experimentally investigated and compared with regard to their excitation behaviour. The experiments are performed on a back-to-back test rig and include quasi-static transmission error measurements under load as well as dynamic torsional vibration measurements. The results show a significant improvement of the excitation behaviour for spur gears with variable tip diameter.

Silicon-based FMCW signal generators: A review

FMCW radars with high resolution necessities the generation of highly linear, low phase noise, and low spur chirp signals with large bandwidth and a short modulation period. This paper reviews recent research progress on silicon-based FMCW signal generators, identifies advances in architecture, fundamental design, performance analysis, and applications of the FMCW synthesizer.

Low spurious optoelectronic oscillator achieved by frequency conversion filtering without deteriorating phase noise.

In order to obtain microwave signals with low spurs and low phase noise, we studied the residual phase noise of the frequency-conversion filtering oscillator and methods to improve its phase noise performance. We first analyze the influence of the dispersion of the intermediate frequency (IF) filter on the residual phase noise in the frequency conversion filtering process. Then, we use an electro-optic modulator to achieve up-conversion in the frequency conversion filtering and extend the intra-cavity delay with an optical fiber after the modulator. This allows the optoelectronic oscillator (OEO) to improve the phase noise performance while having a good suppression of spurs. The spurs suppression ratio of the proposed OEO is 80 dB with a fiber of about 1.6 km in the cavity. The phase noise of the proposed OEO is -130 dBc/Hz at 10 kHz offset from 10 GHz, which is 10 dB lower than our previous work.

Low spur frequency synthesiser using randomly shifted reference spur to higher frequencies

ABSTRACT A low spur frequency synthesiser is proposed based on the frequency-hopping spread spectrum which is employed on the control voltage of the voltage-controlled oscillator. A spur reduction circuit is inserted between the phase-frequency detector and charge pump to randomly shift the spur to higher frequencies to suppress the reference spur. In order to achieve this, the proposed technique uses the time to voltage converter and the voltage to time converter and a linear feedback shift register. Through shifting and randomising the periodic ripples on the control voltage to high frequencies, the amplitude of the reference spur is attenuated. The proposed structure eliminates the need for decreasing bandwidth and reducing the VCO gain to suppress the reference spur. A 2.08–2.22 GHz frequency synthesiser is designed and a post-layout simulation is performed using the 180 nm CMOS technology. The reference spur level of −91.25 dBc is achieved. The presented structure provides an additional spur reduction of 32.88 dB compared to a conventional frequency synthesiser and also provides the best-normalised reference spur rejection in the literature. Settling time is obtained when the output frequency is switched from 2.1 to 2.08 GHz.

Guest Editorial: Rapid Pivot to Gas Crucial for Future Energy Mix

Guest editorial The crash in the oil price during March, caused by oversupply coinciding with an expected large drop in short-term demand because of the COVID-19 pandemic, will cause severe disruption to the industry for at least the next 12–18 months. Whether the low price spurs greater demand for oil when the pandemic subsides, or whether demand for oil continues to drop for the next few years, does not really affect the longer-term trends that we examine in this article. There are numerous views of what the future energy landscape will look like in the next decade and beyond. A common theme throughout is that energy use could switch quite rapidly, from fossil fuels to electrical energy. Many studies, to varying extents, have examined the impact of a primary energy supply that evolves away from oil and coal, and toward renewables. Although a pivot to gas is widely talked about, none of the major oil companies have yet to significantly alter the ratio of gas vs. oil produced. However, all acknowledge that this is essential. There is no easy alternative that can provide cleaner energy at the volume required to sustain a growing world population with an increasing per capita energy demand. Dash for Gas Through our “Rapid Pivot to Gas” analysis, we reviewed a range of forecasts and concluded that a significant and rapid swing to natural gas will be required, in addition to a huge growth in wind and solar power. Global primary energy demand will continue to increase, from 14,300 million tonnes of oil equivalent (MTOE)/year in 2018 to 21,500 MTOE/year in 2040. This rise will be driven by economic growth in non-OECD countries, and much of that increased demand will have to be fulfilled by natural gas. Under this scenario, approximately $20 trillion would need to be invested in natural gas E&amp;P over the next 2 decades. This will also require significant technology advances if we are to use the gas responsibly, including the need for carbon capture and storage (CCS). Even with the phasing out of coal and oil, and a rapid increase in renewables, CO2 emissions would continue to increase until 2025 before starting to decline. The starting point for our projection of how a rapid pivot to gas might occur starts with a decline in coal consumption for environmental reasons, and an unprecedented reduction in oil (liquid hydrocarbons) consumption as transportation rapidly converts to electricity produced from other primary sources of energy. We postulate that conventional crude oil and coal could decline to 1,500 MTOE/year and 1,200 MTOE/year, respectively, by 2040. This is 56% and 68% below 2018 levels. Aggressive growth rates of over 1,000% from 2016 to 2040 have been assumed for new renewables, particularly for wind and solar. In addition to sustained installation of capacity, the uptime and efficiency of new capacity is projected to keep improving for the next 20 years, so that net energy delivered per unit of capacity installed increases continuously. But in relative terms, the overall energy from wind and solar will still be quite small, accounting for less than 10% of total primary energy by 2040.

A Low-Spur MASH Delta-Sigma Modulator With an Adaptive Length Extension Technique

This brief presents a novel multistage noise–shaping (MASH) delta-sigma modulator that has low spurs for all input values by the proposed adaptive length extension technique. Based on the feedforward structure, the accumulators in the proposed MASH are fully utilized to realize an adaptive feedforward gain to compensate for the sequence length loss due to input. The proposed MASH can extend the output sequence length to the maximum under any input, thus to reduce spurs. Simulation results show that the quantization noise of the proposed MASH is distributed widely with no noticeable spurs. Synthesized with 180nm CMOS technology, the increase in hardware cost of the proposed MASH is slight.

A Low-Spur and Intrinsically Aligned IL-PLL With Self-Feedback Injection Locked RO and Pseudo-Random Injection Locked Technique

A novel injection-locked phase locked loop (IL-PLL) with low spur and low phase noise is presented in this paper, in which self-feedback injection locked ring oscillator (SFIL-RO) and pseudo-random injection locked technique (PRILT) are presented. SFIL-RO, of which the oscillation signal is feedback to the input of the pulse generator to generate injection pulse, is proposed to achieve inherently aligned injection timing to decrease the injection spur. Meanwhile, it avoids the risk of suffering from pseudo-locking phenomenon, enhancing the immunity to the PVT variation. The periodicity of conventional injection behavior is broken in proposed PRILT, which essentially reduces the spur. The actual output of the IL-PLL with PRILT is the pseudo-random edge combination of two SFIL-ROs. Thus, the equivalent injection pulse is aperiodic. Calibration circuit is included to cope with the mismatch between two SFIL-ROs. To demonstrate the effectiveness of the proposed SFIL-RO and PRILT on optimizing spur, an IL-PLL was fabricated in SMIC 180 nm CMOS process. Measurement results show the best spur of −67.2 dBc and the RMS jitter of 124 fs are achieved when SFIL-RO and PRILT are activated. The core area was 0.142 mm2 and the power consumption is 6.1 mW from 1.8 V supply voltage.

Design of optimized high precision fractional‐N frequency synthesizer with low spur

AbstractThis article presents a novel multimode cascaded frequency division structure for a low‐spur wide‐bandwidth fractional‐N frequency synthesizer. In order to reduce fractional spur, the new ∆‐∑ modulators are designed as a three‐order structure and each of them is composed of a three‐bit three‐order hybrid feedback ∆‐∑ modulator. Besides, a mixing phase‐locked loop structure is designed to effectively cancel out the VCO cross‐coupling path to reduce spur. The synthesizer implemented in a standard 0.18 μm CMOS process occupies a core area of 0.36 mm2 and generates a frequency ranging from 3 to 6 GHz using 50 MHz~100 MHz oscillator input. Measured results indicate that the fractional spur is lower than −80 dBc and the resolution is higher than 0.001 Hz.

Current pulse shaping technique for low spur fractional‐N phase‐locked loop

Current pulse shaping technique is proposed for low spur fractional-N phase-locked loop, which is realised by a variable amplitude charge pump (VA-CP) and a fixed-position, fixed-width and variable-period pulse generator (FFVPG). The current pulse of VA-CP driven by the FFVPG is shaped to fixed position, fixed width, variable amplitude and variable period for eradicating both reference spurs and fractional spurs. The period of VA-CP's current pulse is T REF during transient and N 1 × T REF during locking status, in which the N 1 should be properly set in order to reduce fractional spurs as far as possible and accelerate locking time. The spur performance of the proposed fractional phase-locked loop is evaluated by analysing the spectrum of tuning voltage when reference frequency is 20 MHz and division ratio is 120.13. Spectre based simulation results show the reference spurs at integer multiplies of 20 MHz is eradicated, and the fractional spurs at 10 MHz and the other fractional frequencies are 19.67 dB and much less than that with the existing technique, which verify the feasibility of this study.

A 3.2-to-3.8 GHz Harmonic-Mixer-Based Dual-Feedback Fractional-N PLL Achieving -65 dBc In-Band Fractional Spur

A harmonic-mixer-based dual-feedback loop architecture for fractional frequency synthesis is proposed in this letter. By performing frequency subtraction instead of frequency division by using the harmonic mixer in the feedback path, the proposed phase-locked loop (PLL) achieves a unity feedback coefficient, which avoids ΔΣ noise amplification by the loop. This leads to low phase noise and low spurs without the use of complex calibration schemes. The proposed architecture is demonstrated with a 3.2-to-3.8GHz fractional-N PLL prototype in a 65-nm bulk CMOS process that achieves a worst-case in-band fractional spur of -65 dBc.

A 39-GHz Frequency Tripler With &gt;40-dBc Harmonic Rejection for 5G Communication Systems in 28-nm Bulk CMOS

The generation of the carrier signal with a very low spur level is a key challenge in all the communication systems, especially those operating at mm-waves, where a frequency multiplier is typically used to break the tradeoff between high frequency of operation and low phase noise. This letter describes a frequency tripler tailored to cover the fifth generation new radio 39-GHz frequency range. By embracing the edge-combining concept, together with the combination of a single-stage polyphase filter and a multipoint injection-locked ring oscillator, the proposed frequency multiplier is able to offer robust and consistent high harmonic rejection ratio over a large fractional bandwidth. Fabricated in 28-nm bulk CMOS technology, the measured frequency multiplier features >40-dBc harmonic rejection over an outstanding 35% fractional bandwidth, while consuming 25 mW only from 0.9-V supply. To the best of our knowledge, the proposed multiplier achieves the highest harmonic rejection among the state-of-the-art multipliers in CMOS and BiCMOS technologies, while having 60% smaller area.

High-performance millimeter-wave synergetic optoelectronic oscillator with regenerative frequency-dividing oscillation technique.

A novel millimeter-wave synergetic optoelectronic oscillator based on regenerative frequency-dividing oscillation and phase-locking techniques is proposed and experimentally demonstrated. The regenerative frequency-dividing oscillator is embedded for millimeter-wave frequency division, and then synergistically oscillates with the optoelectronic oscillator (OEO) due to injection-locking effect. The phase-locking stabilization technique is skillfully utilized in millimeter-wave OEO via commercial analog phase shifter. As a result, a 40-GHz signal is generated featuring low phase noise, high stability and low spurs. The single-sideband phase noise is about -117 dBc/Hz at 10-kHz offset frequency and the spurious suppression ratio reaches more than 80 dBc. The measured overlapping Allan deviation of the proposed synergetic OEO reaches lower than 10-13 at 1024-s averaging time, which is five orders of magnitude lower than free-running millimeter-wave OEO.

Spurious Suppression in Millimeter-Wave OEO With a High- $Q$ Optoelectronic Filter

A millimeter-wave optoelectronic oscillator with low phase noise and low spurs employing ultrahigh $Q$ optoelectronic hybrid band-pass filter is proposed. The 1-MHz pass-band filter in 29.99 GHz with $Q$ value of 30000 has been demonstrated. Based on this ultranarrow band-pass filter, a 29.99-GHz millimeter-wave signal with the spurious suppression ratio more than 83 dB is successfully generated. Besides, the single-sideband phase noise is about −113 dBc/Hz at 10-kHz offset frequency.

A Model for Designing Ultralow Noise Single- and Dual-Loop 10-GHz Optoelectronic Oscillators

A complete model describing both single- and dual-loop optoelectronic oscillators (OEO) is introduced. It is compared to several experimental configurations, with excellent agreement in all cases. The physical insight into noise coupling mechanisms brought by the model further allows us for the design of ultralow noise OEO. Phase noise performances at 10 GHz with a single 1 km delay line and with a dual 1 km/100 m delay lines are reported. An optimized dual loop configuration exhibits low phase noise floor at high offset frequency (–160 dBc/Hz at 100 kHz) and low spur levels (–145 dBc/Hz), here again in close agreement with our model.

A CMOS Charge Pump Circuit with Short Turn-on Time for Low-spur PLL Synthesizers

A charge pump circuit with very short turn-on time is presented for minimizing reference spurs in CMOS PLL frequency synthesizers. In the source switching charge pump circuit, applying proper voltages to the source nodes of the current source FETs can significantly reduce the unwanted glitch at the output current while not degrading the rising time, thus resulting in low spur at the synthesizer output spectrum. A 1.1-1.6 GHz PLL synthesizer employing the proposed charge pump circuit is fabricated in 65 nm CMOS. The current consumption of the charge pump is 490 μA from 1 V supply. Compared to the conventional charge pump, it is shown that the reference spur is improved by 7.5 dB through minimizing the turn-on time. Theoretical analysis is described to show that the measured results agree well with the theory.

A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs

This paper presents a novel high performance, ultra-low power scalable CMOS charge pump (CP) design for analog phase-locked loops (PLLs) fabricated in all-digital nanoscale IC processes. The compact CP circuit uses four minimally-sized transistor switches and a relatively small capacitor for transferring charge within the PLL to adjust the voltage controlled oscillator frequency in the PLL control loop. Unlike the state of the art designs, the proposed CP topology does not use current mirrors, nor does it suffer from traditional mismatch errors due to its unique structure. Additionally, this charge transfer-based CP has the ability to operate at very low supply voltages well below 1 V. The fast switching action of the proposed CP allows for the use of a no-added delay D-flip flop-based phase-frequency detector resulting in a reduced PLL control loop delay and very low reference spurs in the overall PLL design. The proposed CP has been placed in a 0.5---10 GHz PLL, fabricated, and physically tested in an all-digital 40 nm TSMC CMOS process. Additionally, post-silicon measurements of the CP circuit have been completed with a variable 0.2---1.2 V supply and a 50 MHz---1 GHz reference frequency. The proposed CP has an active area of 0.0004 mm2, consumes on average 250 pW power, and has a 0.1°---0.3° phase error, dependent on the PLL frequency of operation.