Abstract

A harmonic-mixer-based dual-feedback loop architecture for fractional frequency synthesis is proposed in this letter. By performing frequency subtraction instead of frequency division by using the harmonic mixer in the feedback path, the proposed phase-locked loop (PLL) achieves a unity feedback coefficient, which avoids ΔΣ noise amplification by the loop. This leads to low phase noise and low spurs without the use of complex calibration schemes. The proposed architecture is demonstrated with a 3.2-to-3.8GHz fractional-N PLL prototype in a 65-nm bulk CMOS process that achieves a worst-case in-band fractional spur of -65 dBc.

Highlights

  • Fractional-N frequency synthesizers are commonly used in applications such as wireless communications where high resolution control of the carrier frequency is essential

  • The design of fractional-N phase locked loops (PLLs) generally faces two issues: phase noise peaking due to the shaped quantization noise from the ∆Σ modulator (DSM) in the multi-modulus divider (MMD), and in-band fractional spurs caused by the quantization noise interacting with the charge-pump (CP) nonlinearity [1]

  • Many different approaches have been proposed to tackle these issues. Works such as [2]–[4] attempt to cancel the deterministic noise from the ∆Σ modulator by using a current DAC [2] or by using a digital-to-time converter [3], [4]. This approach requires gain matching as well as high linearity for the circuit components, which leads to complex calibration schemes such as a least mean square (LMS) algorithm

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Summary

INTRODUCTION

Fractional-N frequency synthesizers are commonly used in applications such as wireless communications where high resolution control of the carrier frequency is essential. Many different approaches have been proposed to tackle these issues Works such as [2]–[4] attempt to cancel the deterministic noise from the ∆Σ modulator by using a current DAC [2] or by using a digital-to-time converter [3], [4]. This approach requires gain matching as well as high linearity for the circuit components, which leads to complex calibration schemes such as a least mean square (LMS) algorithm.

PROPOSED ARCHITECTURE
CIRCUIT IMPLEMENTATION
SIMULATION AND MEASUREMENT RESULTS
CONCLUSION
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