Low-resistivity P-type Substrates Research Articles

Low VF 4H-SiC N-i-P diodes using newly developed low-resistivity p-type substrates

We fabricated 4H-SiC N-i-P (N-intrinsic-P) diodes using newly developed low-resistivity p-type substrates with higher acceptor concentrations than conventional substrate. N-i-P diodes with 10 μm thick n− drift layers were fabricated on both a low-resistivity p-type substrate and a conventional one to investigate the difference in substrate resistance and bipolar degradation with a heavily doped p-type buffer layer. The differential on-resistance of N-i-P diode, using low-resistivity p-type substrates was decreased to one third compared to the conventional case, and the difference was similar to the p-type substrates resistivity. No stacking faults expansion was observed up to 1100 A cm−2. N-i-P diodes with 233 μm thick n− drift layers were fabricated to demonstrate forward characteristics instead of an ultra-high voltage n-channel IGBTs. The forward characteristics of the N-i-P diodes with 233 μm thick n− drift layers at 200 °C showed low on-voltage 6.9 V and low differential on-resistance 32.2 mΩ cm2.

On the determination of the substrate effective doping concentration of irradiated HV-CMOS sensors using an edge-TCT technique based on the Two-Photon-Absorption process

We introduce a new method based on the transient-current technique (TCT) for the radiation tolerance assessment of an n-in-p junction with a deep n-well on a relatively low-resistivity p-type substrate commonly used for HV-CMOS pixel sensors. The transient-current method here employed uses a femtosecond laser to generate excess carriers via a two-photon-absorption (TPA) process. Special attention has been paid to overcome the limitations of the conventional transient-current method based on single-photon-absorption carrier generation when applied to the HV-CMOS sensors. Specifically, we tackle the precise determination of the depletion region boundaries, including the deep-n-well spatial location, needed to calculate the effective doping concentration of the substrate. As illustration, we have applied this new TPA-based method to both a fresh and a neutron irradiated single-pixel deep-n-well diode manufactured in a 180 nm high-voltage CMOS process. In the irradiated device, concurrent with the expected effective acceptor removal in the p-type substrate, an indication of an effective donor removal in the DNW implant was also observed.

Solution Growth of <i>p</i>-Type 4H-SiC Bulk Crystals with Low Resistivity

P-type 4H-SiC bulk crystals have been grown at a high growth rate of 1.0 mm/h by solution growth using Si-Cr-Al based melt. The crystals grown from solution with an Al content of 10at% show low resistivity of 35 mcm, which is two orders of magnitude lower than commercialwafers (Resistivity: 2500 mcm). The low-resistivity crystals have flat surface and few solvent inclusions. These results indicate that solution growth is a suitable method for fabricating low-resistivity p-type substrates with low cost.

Properties of purified direct steam grown silicon thermal oxides

Thermal silicon oxides are known to very effectively passivate silicon surfaces. Choosing a water vapor ambient instead of a dry oxygen atmosphere increases the oxidation rate by about one order of magnitude and considerably reduces process time and costs. State of the art pyrox systems produce steam by pyrolysis of hydrogen and oxygen gas. A new approach is the purification of vaporized deionized (DI) water. In this work we present a direct comparison of both steam generation systems, which are connected to the same quartz tube of an industrial high quality tube furnace. The higher steam saturation of the direct steam process enhances the growth rate by about 20% compared to a pyrolytic steam based process. On low-resistivity p-type substrates, excellent surface recombination velocities of around 25 cm/s are found for both systems after a forming gas anneal. Detailed characterization shows similar physical properties of the oxide layers grown by either steam from pyrolysis or purified steam. Moreover, thermal oxide rear surface passivated silicon solar cells show similar high efficiencies exceeding 18.0% irrespective of the applied steam generation technology.

Very low surface recombination velocity on p-type c-Si by high-rate plasma-deposited aluminum oxide

Aluminum oxide layers can provide excellent passivation for lowly and highly doped p-type silicon surfaces. Fixed negative charges induce an accumulation layer at the p-type silicon interface, resulting in very effective field-effect passivation. This paper presents highly negatively charged (Qox=−2.1×1012 cm−2) aluminum oxide layers produced using an inline plasma-enhanced chemical vapor deposition system, leading to very low effective recombination velocities (∼10 cm s−1) on low-resistivity p-type substrates. A minimum static deposition rate (100 nm min−1) at least one order of magnitude higher than atomic layer deposition was achieved on a large carrier surfaces (∼1 m2) without significantly reducing the resultant passivation quality.

Progress in Low-temperature Surface Passivation of Silicon Solar Cells using Remote-plasma Silicon Nitride

Using a remote-plasma technique as opposed to the conventional direct-plasma technique, significant progress has been obtained at ISFH in the area of low-temperature surface passivation of p-type crystalline silicon solar cells by means of silicon nitride (SiN) films fabricated at 350–400°C in a plasma-enhanced chemical vapour deposition system. If applied to the rear surface of the low-resistivity p-type substrates, the remote-plasma SiN films provide outstanding surface recombination velocities (SRVs) as low as 4 cm s−1, which is by a clear margin the lowest value ever obtained on a low-resistivity p-Si wafer passivated by a solid film, including highest quality thermal oxides. Compared to direct-plasma SiN films or thermally grown oxides, the remote-plasma films not only provide significantly better SRVs on low-resistivity p-silicon wafers, but also an enormously improved stability against ultraviolet (UV) light. The potential of these remote-plasma silicon nitride films for silicon solar cell applications is further increased by the fact that they provide a surface passivation on phosphorus-diffused emitters which is comparable to high-quality thermal oxides. Furthermore, if combined with a thermal oxide and a caesium treatment, the films induce a UV-stable inversion-layer emitter of outstanding electronic quality. Due to the low deposition temperature and the high refraction index, these remote-plasma SiN films act as highly efficient surface-passivating antireflection coatings. Application of these films to cost-effective silicon solar cell designs presently under development at ISFH turned out to be most successful, as demonstrated by diffused p-n junction cells with efficiencies above 19%, by bifacial p-n junction cells with front and rear efficiencies above 18%, by mask-free evaporated p-n junction cells with efficiencies above 18% and by MIS inversion-layer cells with a new record efficiency of above 17%. All cells are found to be stable during a UV test corresponding to more than 4 years of glass-encapsulated outdoor operation. © 1997 John Wiley & Sons, Ltd.

A new high-performance lateral insulated gate bipolar transistor formed on Quasi-SOI

In the proposed LIGBT/Quasi-SOI, the buried oxide layer of the Quasi-SOI is partially removed at the bottom of the channel region and this channel region is directly connected to the low-resistivity p-type substrate. This structure significantly reduces the base resistance of the parasitic npn-bipolar transistor and significantly increases its latch up current. Simulation of the electrical characteristics of the proposed LIGBT/Quasi-SOI showed that, at a substrate resistivity of 20 m/spl Omega//spl middot/cm, latch up free operation can be obtained.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fully integrated, monolithic, cryogenic charge sensitive preamplifier using N-channel JFETs and polysilicon resistors

An N-channel JFET process technology for integrated charge sensitive preamplifiers has been developed. The process integrates multiple pinch-off voltage JFETs fabricated in an n-type epitaxial layer on a low resistivity p-type substrate. The process also incorporates polysilicon resistors integrated on the same die as the JFETs. The optimized polysilicon resistors exhibit 1/f noise nearly as good as metal film resistors at the same current. Results for the integrated amplifier are discussed. >