Low-power Viterbi Decoder Research Articles

Sleepy keeper style based Low Power VLSI Architecture of a Viterbi Decoder applying for the Wireless LAN Operation sustainability

Remarkable progress in the field of wireless communication has created a research interest for Viterbi decoder with long duration of battery life, low power dissipation and portabilty in the application. Such a low power Viterbi decoder is required in the area of high speed data transfer application like communication in the convolutional coding for error free inforamtion. This article propose two strategies to enhance the execution of the decoder by circuit level design of the Viterbi decoder utilizing a sleepy keeper method with additional leakage current control transistors, which decreases the leakage power dissipation. Then at the survivor memory unit the variation is done by the usage of modified resister exchange method with search space pruning. The Simulation of the work at the semiconductor level is done with 90 nm TSMC T-SPICE and SPICE netlist is used to create the simscape application of decoder which is applied in the Matlab Communication toolbox. The outcome of the system determines that the proposed sleepy keeper Viterbi Decoder in WLAN application has a reduction of 0.24 % with QPSK and 0.13 % reduction with QAM. Also, the SNR is found to be improved at a rate of 0.5db when compared with code based Viterbi decoder.

Wave Pipelined VLSI Architecture for a Viterbi Decoder Using Self Reset Logic with 0.65nm Technology

In 3G mobile terminals the Viterbi Decoder consumes approximately one third of the power consumption of a base band mobile transceiver. Viterbi decoders employed in digital wireless communications are complex and dissipate large power. A low power Viterbi decoder is designed in circuit level using self reset logic and wave pipelining technique is implemented for high speed operation. The Viterbi decoder consists of four units like branch metric unit, add compare and select unit and the survivor path memory unit. All these units are designed using the self reset logic and wave pipelining, and simulated with its layout using MICROWIND TOOL in the 0.65nm technology, 1.8V Vdd and at a frequency of 10GHz. The simulation result shows that the power consumption is reduced by 70.55% and the speed of the circuit is increased by 45.83% compared to the Single Rail Domino Logic for constraint length of K =3 to 7.

A Fast and Efficient Add-Compare-Select Structure Using Hybrid Logic Asynchronous Pipeline Design

Convolutional or trellis codes are today widely used in digital communication networks and multimedia broadcasting systems. TheViterbi decoder is commonly used for decoding trellis codes due to its excellent forward error correction performance. High-performance and low-power Viterbi decoders are in great demand in the communication industry. Despite several significant developments in decoder design and architecture in the past decade, the issue of latency and power dissipation still remains a challenge requiring further investigation and innovation. This paper proposes arobust deep-pipelined Add-Compare-Select (ACS) Unit, based on a hybrid logic asynchronous pipeline design method. The ACS operation forms the primary deadlock on the performance of the decoder hardware. With the proposed structure, the ACS units and hence Viterbi Decoder operate at a 323.3% higher throughput with 76.4% reduced latency and 86.6% reduced power consumption, when compared with QDI based realization of the ACS unit.

FPGA Implementation of High Speed and Low Power Viterbi Decoder Using Reverse Algorithm of Convolution Encoder

FPGA Implementation of High Speed and Low Power Viterbi Decoder Using Reverse Algorithm of Convolution Encoder

Implementation of Low-Power Adaptive Viterbi Decoder for Wireless Communication

There has been a surge of research activities in the field of wireless communication which sweep of the communications industry over the few past decades. This has prone to the emerging technologies for effective communication over wireless channels. The need of data transmission rate was increased by shutting the door of noise. Thus the effects of noise in digital data transmission are reduced drastically by the use of error-detecting and correcting convolutional codes. In this paper, the decoding techniques for convolutional codes, Viterbi algorithm, and adaptive Viterbi algorithm which is based on strongly connected trellis was proposed. The Viterbi algorithm achieves its optimum performance in BER. The low power design technique, Adaptive Viterbi algorithm is applied to the decoder design to improve its power efficiency. This adaptive technique has been implemented on a FPGA and demonstrates a significant power saving at low noise levels. Viterbi decoder and adaptive Viterbi decoder was compared in terms of BER performance, which are also developed in MATLAB and FPGA. The proposed algorithm reduces the average number of ACS computations up to 70% compared to normal Viterbi algorithm, with the same BER performance. Also the improvement in BER performance was compared for different constraint lengths.

Low-power multi-standard Viterbi decoder for wireless communication applications

A Viterbi code is a type of the well-known error correcting code (ECC), which provides a robust error control methodology for wireless communication systems. It can efficiently reduce the bit error rate of the receiver and hence the reliability of the receiver is improved at data fidelity. This paper presents a novel low-power Viterbi decoder (VD) with a four-bit soft decision. To provide a multi-standard ECC processor, this study proposes a code rate 1/2 and 1/3 of VD used in software-defined radio systems for the hardware accelerator. Based on the proposed Viterbi decoding scheme, the survivor memory can be eliminated totally. This scheme achieves energy savings of approximately 50% of the total power dissipation and obtains a lower latency than that of most classical VDs. Furthermore, to avoid overflow occurrences in the add-compare-select unit (ACSU), a normalised mechanism is proposed, which only uses simple shifters and selection operations to reduce the design complexity. Finally, because it is designed with a 0.18 μm complementary metal-oxide-semiconductor technology, the proposed chip uses approximately 26.2 K gates, and its power consumption is approximately 11 mW at 73 MHz.

Speed, Noise Immunity, Power Consumption and Area Comparison between Different Approaches of Low-Power Viterbi Decoder for Digital Wireless Communication Applications

Noise immunity and speed are two vital issues for designing encoding-decoding system for wireless communication. Convolutional coding is widely used in wireless communication system for its error correction property. For the decoding purpose of Convolutional coding Viterbi decoder is used. Core module of Viterbi decoder is Adder-Comparator-Selector (ACS) which takes approximately 70% of total power consumption. So, Adder-Comparator-Selector (ACS) module is transformed into Comparator-Selector-Adder CSA) module for power saving. Reduction of Hamming Distance Logic Circuitry for branch metric calculation also saving power but enhances the packing density of the circuit. In this paper the comparison between ACS and CSA is not only described in terms of power reduction and area but also speed and noise immunity are compared. Basically there are three types of Viterbi decoders: namely Register Exchange, Shift Update and Selective Update. These decoders do not follows the parallelism and pipelining concept but folding cascaded designing of Viterbi Decoder supports parallelism which enhance the speed of the system. This paper gives a new idea of logic reduction of Viterbi Decoder as well as comparison of different Viterbi decoders in different aspects.

Design and Simulation of a Low Power Viterbi Decoder using Constraint Length Nine

Viterbi Decoder is the dominant module to determining the power consumption of the system. High speed and low power design of Viterbi Decoder with data rate1/2 and convolution encoding with a constraint length K = 9 is presented in this paper. The Proposed Viterbi decoder can be reduce the power consumption without reducing the decoding speed and also increases the length of the bits. The operating frequency of convolution encoder and Viterbi decoded is 306.65MHz and power consumption is 45.01Mw using Xpower tools in Xilinx and Spartan 3E FPGA kit.

An Efficient Low Power Viterbi Decoder Design using T-algorithm

This paper presents an efficient Low-Power Viterbi Decoder Design using T-algorithm. It implements the viterbi decoder using T-algorithm for decoding a bit-stream encoded by a corresponding forward error correction convolutional encoding system. A lot of digital communication systems incorporated a viterbi decoder for decoding convolutionally encoded data. The viterbi decoder is able to correct errors in received data caused by channel noise. We proposed an architecture implementing a Viterbi Decoder with Talgorithm deployed with threshold generator unit and purge unit to reduce the number of states which reduce power consumption. We propose modified architecture for the survivor Metric Unit to reduce the memory Access power during the trace back operation. The proposed viterbi decoder is carried out for rate-1/2 with a standard constraint length 7. The Synthesis results will be done using cadence RTL Encounter Tool. For ASIC synthesis, we use TSMC 45nm CMOS Process. The architecture which reduces the complexity and power Consumption by as much as 70% without effecting the decoding speed. General Terms

A Low Power VITERBI Decoder Design With Minimum Transition Hybrid Register Exchange Processing for Wireless Applications

This work proposes the low power implementation of Viterbi Decoder. Majority of viterbi decoder designs in the past use simple Register Exchange or Traceback method to achieve very high speed and low power decoding respectively, but it suffers from both complex routing and high switching activity. Here simplification is made in survivor memory unit by storing only m-1 bits to identify previous state in the survivor path, and by assigning m-1 registers to decision vectors. This approach eliminates unnecessary shift operations. Also for storing the decoded data only half memory is required than register exchange method. In this paper Hybrid approach that combines both Traceback and Register Exchange schemes has been applied to the viterbi decoder design. By using distance properties of encoder we further modified to minimum transition hybrid register exchange method. It leads to lower dynamic power consumption because of lower switching activity. Dynamic power estimation obtained through gate level simulation indicates that the proposed design reduces the power dissipation of a conventional viterbi decoder design by 30%.

Error-Resilient Low-Power Viterbi Decoder Architectures

Three low-power Viterbi decoder (VD) architectures are presented in this paper. In the first, limited decision errors are introduced in the add-compare-select units (ACSUs) of a VD to reduce their critical path delays so that they can be operated at lower supply voltages without incurring timing errors. Power savings in this design can reach 58% and 44% with a 0.15 dB coding loss under reduced voltage operation and process variations, respectively, with adaptive supply voltage and adaptive body biasing applied to avoid timing errors. In the other two designs, we permit data-dependent timing errors to occur whenever a critical path in the ACSU is excited. Algorithmic noise-tolerance (ANT) is then applied to correct for these errors. Power reduction in these schemes is achieved by either overscaling the supply voltage [voltage overscaling (VOS)] or designing at the nominal process corner and supply voltage (average-case design). Two techniques are proposed to develop efficient estimators for error-correction and achieving increased robustness to timing based errors. The first is based on reduced-precision redundancy and the second on state clustering. The first can achieve up to 40% and 25% power savings under VOS and process variations with loss in coding gain of 1.1 and 1.2 dB, respectively, in a 130-nm CMOS process. The second can achieve up to 71% and 62% power savings under VOS and process variations, respectively, at a loss in coding gain of 0.8 and 0.6 dB, respectively. Under process variations, the designs achieve 16-33X improvement in bit error-rate (BER) performance at a signal-to-noise ratio (SNR) of 2 dB.

A Low Power and High Speed Viterbi Decoder Based on Deep Pipelined, Clock Blocking and Hazards Filtering

A high speed and low power Viterbi decoder architecture design based on deep pipelined, clock gating and toggle filtering has been presented in this paper. The Add-Compare-Select (ACS) and Trace Back (TB) units and its sub circuits of the decoder have been operated in deep pipelined manner to achieve high transmission rate. The Power dissipation analysis is also investigated and compared with the existing results. The techniques that have been employed in our low-power design are clock-gating and toggle filtering. The synthesized circuits are placed and routed in the standard cell design environment and implemented on a Xilinx XC2VP2fg256-6 FPGA device. Power estimation obtained through gate level simulations indicated that the proposed design reduces the power dissipation of an original Viterbi decoder design by 68.82% and a speed of 145 MHz is achieved.

Low-Power Limited-Search Parallel State Viterbi Decoder Implementation Based on Scarce State Transition

In this paper, a low-power Viterbi decoder design based on scarce state transition (SST) is presented. A low complexity algorithm based on a limited search algorithm, which reduces the average number of the add-compare-select computation of the Viterbi algorithm, is proposed and seamlessly integrated with the SST-based decoder. The new decoding scheme has low overhead and facilitates low-power implementation for high throughput applications. We also propose an uneven-partitioned memory architecture for the trace-back survivor memory unit to reduce the overall memory access power. The new Viterbi decoder is designed and implemented in TSMC 0.18-mum CMOS process. Simulation results show that power consumption is reduced by up to 80% for high throughput wireless systems such as Multiband-OFDM Ultra-wideband applications.

FPGA design and implementation of a low-power systolic array-based adaptive Viterbi decoder

In this paper, by modifying the well-known Viterbi algorithm, an adaptive Viterbi algorithm that is based on strongly connected trellis decoding is proposed. Using this algorithm, the design and a field-programmable gate array implementation of a low-power adaptive Viterbi decoder with a constraint length of 9 and a code rate of 1/2 is presented. In this design, a novel systolic array-based architecture with time multiplexing and arithmetic pipelining for implementing the proposed algorithm is used. It is shown that the proposed algorithm can reduce by up to 70% the average number of ACS computations over that by using the nonadaptive Viterbi algorithm, without degradation in the error performance. This results in lowering the switching activities of the logic cells, with a consequent reduction in the dynamic power. Further, it is shown that the total power consumption in the implementation of the proposed algorithm can be reduced by up to 43% compared to that in the implementation of the nonadaptive Viterbi algorithm, with a negligible increase in the hardware.

Effects of signal-dependant errors on the performance of switched-current Viterbi decoders

Analog current-mode circuits including switched-current (SI) methods can he employed beneficially to implement high-speed, low-power Viterbi decoders for convolutional codes. Unfortunately, signal-dependent errors due to charge injection tend to limit the application of these methods to relatively small constraint-length decoders. This paper presents a technique for reducing the effects of charge injection on system performance. As a result, the use of SI techniques can be extended to the realization of larger Viterbi decoders, including the type conventionally employed in satellite communications.

A 2-Mb/s 256-state 10-mW rate-1/3 Viterbi decoder

This paper presents a low-power bit-serial Viterbi decoder chip with the code rate r=1/3 and the constraint length K=9 (256 states) for next generation wireless communication applications. The architecture of the add-compare-select (ACS) module is based on the bit-serial arithmetic and implemented with the pass transistor logic circuit. A cluster-based ACS placement and state metric routing topology is described for the 256 bit-serial ACS units, which achieves very high area efficiency. In the trace-back operation, a power efficient trace-back scheme, allowing higher memory read access rate than memory write in a time-multiplexing method, is implemented to reduce the number of iterations required to generate a decoded output. In addition, a low-power application-specific memory suitable for the function of survivor path memory has also been developed. The chip's core, implemented using 0.5-/spl mu/m CMOS technology, contains approximately 200 K transistors and occupies 2.46 mm by 4.17 mm area. This chip can achieve the decode rate of 20 Mb/s under 3.3 V and 2 Mb/s under 1.8 V. The measured power dissipation at 2 Mb/s under 1.8 V is only about 9.8 mW. The Viterbi decoder presented here can be applied to next generation wide-band code division multiple access (W-CDMA) systems.

Reduction of effects of signal-dependent errorsin current-mode analogue Viterbi decoders

Current-mode analogue techniques can be employed to realise high-speed, low-power Viterbi decoders. However, signal dependent errors due to charge injection tend to limit the application of these methods to small decoders. A technique is presented for reducing the effects of charge injection on the system performance.

Low-power CMOS and BiCMOS circuits for analog convolutional decoders

Analog techniques have been proposed as a method of realizing high-speed low-power Viterbi decoders, mostly for use in digital magnetic recording applications. However, such methods can also be used in more general applications of the Viterbi algorithm, such as convolutional decoding. We describe two current-mode analog circuits for use in such applications. These circuits operate in excess of 100 MHz, and consume less than 4 mW per state, with 2.8-V supply rails when realized in 0.8-/spl mu/m technology.

Low-power Viterbi decoder for CDMA mobile terminals

An efficient state-sequential very large scale integration (VLSI) architecture and low-power design methodologies ranging from the system-level to the layout-level are presented for a large-constraint-length Viterbi decoder for code division multiple access (CDMA) digital cellular/personal communication services (PCS) applications. The low-power design approaches are also applicable to many other systems and algorithms. VLSI implementation issues and prototype fabrication results for a state-sequential Viterbi decoder for convolutional codes of rate 1/2 and constraint-length 9 are also described. The chip's core, consisting of approximately 65 k transistors, occupies 1.9 mm by 3.4 mm in a 0.8-/spl mu/m triple-layer-metal n-well CMOS technology. The chip's measured total power dissipation is 0.24 mW at a 14.4 kb/s data-rate with 0.9216 MHz clocking at a supply voltage of 1.65 V. The Viterbi decoder presented here is the lowest power and smallest area core in its class, to the best of our knowledge.

Design of a Viterbi decoder with low power usingminimum-transition traceback scheme

The authors propose a novel traceback scheme for the implementation of a low power Viterbi decoder. With minor modification of a conventional traceback scheme, the memory access count needed to perform the traceback function can be reduced by a factor of /spl sim/5.0-10.0 over the conventional traceback scheme. Experimental results confirm the efficiency of the proposed scheme.