Low-power Transistors Research Articles

Phonon-assisted charge carriers thermalization in semiconductor Si and metallic silicide NiSi2, CoSi2: A non-adiabatic molecular dynamics study

Recently, the cold source field-effect transistor (CSFET) has emerged as a promising solution to overcome Boltzmann tyranny in its ballistic regime, offering a steep-slope subthreshold swing (SS) of less than 60 mV/decade. However, challenges arise due to scattering, particularly from inelastic scattering, which can lead to significant degradation in SS through cold carrier thermalization. In this study, we delve into the theoretical investigation of the electronic excitation/relaxation dynamic process using the state-of-the-art nonadiabatic molecular dynamics (NAMD) method. The mixed quantum-classical NAMD proves to be a powerful tool for comprehensively analyzing cold carrier thermalization and transfer processes in semiconductor Si, as well as metallic silicides (NiSi2 and CoSi2). The approach of mixed quantum-classical NAMD takes into account both carrier decoherence and detailed balance, enabling the calculation of thermalization factors, relaxation times, scattering times, and scattering rates at various energy levels. The thermalization of carriers exhibits a gradual increase from low to high energy levels. Achieving partial thermalization from the ground state to reach the thermionic current window occurs within a sub-100 fs time scale. Full thermalization across the entire energy spectrum depends sensitively on the barrier height, with the scattering rate exponentially decreasing as the energy of the out-scattering state increases. Notably, the scattering rate of NiSi2 and CoSi2 is two orders of magnitude higher than that of Si, attributed to their higher density of states compared to Si. This study not only provides insights into material design for low-power tunnel field-effect transistors but also contributes valuable information for advancing CSFET in emerging technologies.

Bionic Scotopic Adaptation Transistors for Nighttime Low Illumination Imaging.

Human vision excels in perceiving nighttime low illumination due to biological feedforward adaptation. Replicating this ability in biomimetic vision using solid-state devices has been highly sought after. However, emulating scotopic adaptation, entailing a confluence of efficient photoexcitation and dynamic carrier modulation, presents formidable challenges. Here, we demonstrate a low-power and bionic scotopic adaptation transistor by coupling a light-absorption layer and an electron-trapping layer at the bottom of the semiconducting channel, enabling simultaneous achievement of efficient generation of free photocarriers and adaptive carrier accumulation within a single device. This innovation empowers our transistor to exhibit sensitivity-potentiated characteristics after adaptation, detecting scotopic-level illumination (0.001 lx) with exceptional photosensitivity up to 103 at low voltages below 2 V. Moreover, we have successfully replicated diverse scotopic vision functions, encompassing time-dependent visual threshold enhancement, light intensity-dependent adaptation index, imaging contrast enhancement for nighttime low illumination imaging, opening an opportunity for artificial night vision.

Boltzmann Switching MoS2 Metal-Semiconductor Field-Effect Transistors Enabled by Monolithic-Oxide-Gapped Metal Gates at the Schottky-Mott Limit.

A gate stack that facilitates a high-quality interface and tight electrostatic control is crucial for realizing high-performance and low-power field-effect transistors (FETs). However, when constructing conventional metal-oxide-semiconductor structures with two-dimensional (2D) transition metal dichalcogenide channels, achieving these requirements becomes challenging due to inherent difficulties in obtaining high-quality gate dielectrics through native oxidation or film deposition. Here, a gate-dielectric-less device architecture of van der Waals Schottky gated metal-semiconductor FETs (vdW-SG MESFETs) using a molybdenum disulfide (MoS2) channel and surface-oxidized metal gates such as nickel and copper is reported. Benefiting from the strong SG coupling, these MESFETs operate at remarkably low gate voltages, <0.5V. Notably, they also exhibit Boltzmann-limited switching behavior featured by a subthreshold swing of ≈60mVdec-1 and negligible hysteresis. These ideal FET characteristics are attributed to the formation of a Fermi-level (EF) pinning-free gate stack at the Schottky-Mott limit. Furthermore, authors experimentally and theoretically confirm that EF depinning can be achieved by suppressing both metal-induced and disorder-induced gap states at the interface between the monolithic-oxide-gapped metal gate and the MoS2 channel. This work paves a new route for designing high-performance and energy-efficient 2D electronics.

Integration of Ultrathin Hafnium Oxide with a Clean van der Waals Interface for Two-Dimensional Sandwich Heterostructure Electronics.

Integrating high-κ dielectrics with a small equivalent oxide thickness (EOT) with two-dimensional (2D) semiconductors for low-power consumption van der Waals (vdW) heterostructure electronics remains challenging in meeting both interface quality and dielectric property requirements. Here, we demonstrate the integration of ultrathin amorphous HfOx sandwiched within vdW heterostructures by the selective thermal oxidation of HfSe2 precursors. The self-cleaning process ensures a high-quality interface with a low interface state density of 1011-1012 cm-2 eV-1. The synthesized HfOx displays excellent dielectric properties with an EOT of ∼1.5 nm, i.e., a high κ of ∼16, an ultralow leakage current of 10-6 A/cm2, and an impressively high breakdown field of 9.5 MV/cm. This facilitates low-power consumption vdW heterostructure MoS2 transistors, demonstrating steep switching with a low subthreshold swing of 61 mV/decade. This one-step integration of high-κ dielectrics into vdW sandwich heterostructures holds immense potential for developing low-power consumption 2D electronics while meeting comprehensive dielectric requirements.

Compact K-Band Current Mode Tunable Active Only Bandpass Filter Using 32 nm CNTFET-Based MOCCCII

A low-power and compact carbon nanotube field-effect transistor (CNTFET)-based [Formula: see text]-band electronically tunable band-pass filter (BPF) is presented. The filter is designed using second-generation multiple-output current-controlled current conveyor (MOCCCII). The presented active only current-mode BPF employs three MOCCCIIs and two CNTFETs as capacitors. This BPF can be tuned by varying the parasitic resistance of MOCCCIIs via the control current. The designed current-mode tunable BPF is simulated in an advanced design system (ADS) using the Stanford CNTFET model with the extension of noise and manufacturing process variation. The filter achieves a 21–23 GHz tuning frequency range, with a minimum noise figure of about 11.09 dB. The 1-dB compression point and input-referenced third-order intercept point are −19.28 and −8.4 dBm, respectively. This compact filter consumes only 145.7 [Formula: see text] W power at ± 0.5 V supply voltage at room temperature. The temperature analysis shows good thermal stability. The Monte Carlo analysis demonstrates the good process variation stability of the filter. The suggested BPF can be thought of as the first fully active BPF that is a candidate for [Formula: see text]-band communication applications with future advances in the fabrication process for CNTFET.

Observation of stabilized negative capacitance effect in hafnium-based ferroic films

A negative capacitance (NC) effect has been proposed as a critical pathway to overcome the ‘Boltzmann tyranny’ of electrons, achieve the steep slope operation of transistors and reduce the power dissipation of current semiconductor devices. In particular, the ferroic property in hafnium-based films with fluorite structure provides an opportunity for the application of the NC effect in electronic devices. However, to date, only a transient NC effect has been confirmed in hafnium-based ferroic materials, which is usually accompanied by hysteresis and is detrimental to low-power transistor operations. The stabilized NC effect enables hysteresis-free and low-power transistors but is difficult to observe and demonstrate in hafnium-based films. This difficulty is closely related to the polycrystalline and multi-phase structure of hafnium-based films fabricated by atomic layer deposition or chemical solution deposition. Here, we prepare epitaxial ferroelectric Hf0.5Zr0.5O2 and antiferroelectric ZrO2 films with single-phase structure and observe the capacitance enhancement effect of Hf0.5Zr0.5O2/Al2O3 and ZrO2/Al2O3 capacitors compared to that of the isolated Al2O3 capacitor, verifying the stabilized NC effect. The capacitance of Hf0.5Zr0.5O2 and ZrO2 is evaluated as −17.41 and −27.64 pF, respectively. The observation of the stabilized NC effect in hafnium-based films sheds light on NC studies and paves the way for low-power transistors.

Carrier type and density dependence of impact ionization characteristics in WSe2.

The impact ionization process offers advantages in achieving low-power and high-speed switching in transistors and also provides high internal gain for photodetectors. We investigate the density dependence of both electron- and hole-initiated impact ionization in WSe2. We observe a record-low critical electric field for impact ionization and a large multiplication factor in WSe2 when the impact ionization is initiated by holes, particularly near a charge-neutral point. As the carrier density increases, the impact ionization decreases, which is attributed to the increase in Fermi energy and the weakening of the carrier-carrier interaction by increasing the screening effect. To understand the role of screening effects on the impact ionization, we examine the carrier scatterings of several scattering sources and the rate of change of the channel current with respect to the drain source voltage, ΔIDS/ΔVDS. We obtain the optimal conditions for impact ionization and apply these findings to fabricate avalanche photodetectors (APDs). This study proposes that the performance of low-power transistors or APDs, utilizing impact ionization, can be enhanced under optimized conditions by examining and controlling specific external parameters.

Horizontally aligned ALD-SnO films grown on SiO2-passivated high-k HfO2 dielectrics for high-mobility and low-power P-channel thin-film transistor

The fabrication of SiO2-passivated HfO2 (HfO2/SiO2) as a high-k dielectric stack for high-mobility, low-power p-channel SnO thin-film transistors (TFTs) is reported herein. To achieve superior TFT performance, a high-k HfO2 film was introduced by replacing the thermally-grown SiO2. However, the atomic layer deposited (ALD)-SnO films grown on the HfO2 substrate exhibited a very rough surface and out-of-plane tilted SnO (001), resulting in a significantly degraded field-effect mobility (μFE) compared with that of SnO TFTs based on an SiO2 gate dielectric. Therefore, 1–10 nm-thick ALD-SiO2 passivation layers were deposited on high-k HfO2 to effectively improve the surface morphology of the ALD SnO. Furthermore, SiO2 passivation enabled the control of the crystallographic orientation of the ALD SnO. Through SiO2 passivation, the horizontally aligned SnO (00l) planes parallel to the substrate demonstrated significantly improved μFE characteristics. The optimized SnO TFTs fabricated with HfO2/SiO2 stacks exhibited excellent carrier transport and low-voltage operation characteristics, with μFE of 2.3 cm2/V·s, subthreshold swing of 0.5 V/dec, on-to-off drain current ratio of 1.4 × 104, and Vth of −1.2 V.

Modified Efficient Energy Conversion System Based on PMSG with Magnetic Flux Modulation

The article presents the solution of a power rectifier system dedicated to cooperating with an electric generator based on a special synchronous generator, which can be used in wind or water energy systems. In this generator, a pair of three-phase windings in a stator is utilized. One of the windings is connected in a star, and the second one is connected in a delta configuration. Two six-pulse uncontrolled (diode) rectifiers are included at the outputs of the windings. The rectifiers are coupled by a pulse transformer. The primary windings of this transformer are supplied by a power-electronics current source called a current modulator. With the help of this current modulator, the quasi-sinusoidal magnetomotive force (mmf) in the stator of the machine can be obtained. Additionally, to improve the efficiency of the described system, the low-power transistor rectifier, which is connected to the DC bus of the current modulator, has been used. With the help of this converter, it is possible to control and stabilize the voltage level in a DC circuit. It works, in this case, in inverter mode. The principle of working and elaborated control methods of the current modulator and the additional rectifier are presented. Selected results of simulation and experimental tests are also presented.

Transparent polymer nanoheterostructure films for flexible low-power organic transistors with high mobility, decent photostability, and ultralong-term air stability

Organic field-effect transistors (OFETs) are promising candidates for flexible electronic devices, but their instability remains a huge challenge that should be solved for practical applications. It is very difficult to achieve high-performance energy-efficient OFETs with good photostability and ultralong-term air stability. Here, a novel type of transparent and stable polymer films comprising p-type nanofibrous semiconductor and insulating polystyrene is developed, forming the nanoscale cross-interconnected heterostructures. The nanoheterostructure films as channel layers enable flexible low-power OFETs to achieve highly improved mobilities up to 6.78 cm2 V−1 s−1 at a low-operating voltage of −0.5 V despite the small semiconductor content, and the substantial amount of inert insulators can effectively prevent external factors such as light, moisture, and oxygen from interfering with the semiconductor layer. As results, the flexible OFETs using these nanoheterostructure films show slight performance changes under different light illuminations even by three laser beams, and their unencapsulated devices retain excellent performance even after over 450 days of ultralong-term and high-humidity air exposure. These findings demonstrate that nanoscale heterostructure films of polymer semiconductors and insulators constitute a simple yet efficient strategy for improving the OFET stability, which holds great promise for developing high-performance durable and energy-saving devices in flexible and transparent electronics.

Rational tuning of the cation ratio in metal oxide semiconductor nanofibers for low-power neuromorphic transistors

Wide-bandgap metal oxide semiconductor (MOS) nanofiber neuromorphic transistors (NFNTs) can be potentially used to construct low-power bio-inspired artificial circuits. However, the cation ratio of MOS used for NFNTs is mostly adopted without detailed reasons in literature. In this study, we have for the first time focused on systematically tuning the cation ratio of indium zinc oxide (InZnO)-based NFNTs, fabricated by a low-cost electrospinning technique combined with a facile nanofiber transfer process. These electrical-driven NFNTs based on double-cation InZnO nanofibers can greatly simplify experimental procedures. Among the cation ratios of InxZn1−xO (x = 0.6, 0.7, 0.8, 0.9), we found that NFNTs based on In0.7Zn0.3O exhibited the lowest excitatory postsynaptic currents and offered electrical benefits for low-power operations and synaptic function simulations. The rational tuning of MOS nanofiber composition opens the door for high-performance low-power NFNTs.

Buried graphene heterostructures for electrostatic doping of low-dimensional materials

The fabrication and characterization of steep slope transistor devices based on low-dimensional materials requires precise electrostatic doping profiles with steep spatial gradients in order to maintain maximum control over the channel. In this proof-of-concept study we present a versatile graphene heterostructure platform with three buried individually addressable gate electrodes. The platform is based on a vertical stack of embedded titanium and graphene separated by an intermediate oxide to provide an almost planar surface. We demonstrate the functionality and advantages of the platform by exploring transfer and output characteristics at different temperatures of carbon nanotube field-effect transistors with different electrostatic doping configurations. Furthermore, we back up the concept with finite element simulations to investigate the surface potential. The presented heterostructure is an ideal platform for analysis of electrostatic doping of low-dimensional materials for novel low-power transistor devices.

Solution processed rare-earth doped high-k dielectrics for low-power IGZO transistors

Low-power metal oxide transistors are highly required in displays, logic circuit and sensors. High quality gate dielectrics with the properties of high dielectric constant, smooth surface, and excellent insulating performance are critical to realize the above mentioned transistors. In this work, we present a universal strategy by using rare-earth (RE) elements (Y, Er and Yb) as dopants to improve the dielectric properties of zirconia film for low-power transistors. Additionally, all the dielectric films are prepared by solution process, which is compatible with low-cost and large-area manufacturing technology. The leakage current densities of zirconia films decrease from 1.27 × 10−5 A/cm2 to 2.8 × 10−7 A/cm2, 6.6 × 10 − 7 A/cm2, and 4.3 × 10−7 A/cm2 by doping a small amount of Y, Er, and Yb in zirconia films, respectively. Furthermore, bottom-gate top-contact indium-gallium-zinc oxide (IGZO) transistors with RE-doped zirconia dielectrics show one order improved current on/off (∼104) ratio and achieve one order improvement in mobility (3.11, 2.85, 2.75 cm2V−1S−1 for Y-, Er-, Yb-doped devices respectively) compared with that of pure zirconia film based devices (0.30 cm2V−1S−1). Moreover, the subthreshold swing (SS) of TFTs based on RE-doped and undoped ZrO2 dielectric films are calculated (0.2, 0.36, 0.21 V/dec for Y-, Er-, Yb-doped devices respectively, and 0.51 V/dec for undoped devices) This study demonstrates the validity of RE ions as dopants in gate dielectrics to achieve high-performance low-power metal oxide transistors.

Enhancement of Carrier Mobility in Semiconductor Nanostructures by Carrier Distribution Engineering

Two-dimensional (2D) van der Waals semiconductors are appealing for low-power transistors. Here, we show the feasibility in enhancing carrier mobility in 2D semiconductors through engineering the vertical distribution of carriers confined inside ultrathin channels via symmetrizing gate configuration or increasing channel thickness. Through self-consistently solving the Schrödinger–Poisson equations, the shapes of electron envelope functions are extensively investigated by clarifying their relationship with gate configuration, channel thickness, dielectric permittivity, and electron density. The impacts of electron distribution variation on various carrier scattering matrix elements and overall carrier mobility are insightfully clarified. It is found that the carrier mobility can be generally enhanced in the dual-gated configuration due to the centralization of carrier redistribution in the nanometer-thick semiconductor channels and the rate of increase reaches up to 23% in HfO2 dual-gated 10-layer MoS2 channels. This finding represents a viable strategy for performance optimization in transistors consisting of 2D semiconductors.

High-performance and low-power source-gated transistors enabled by a solution-processed metal oxide homojunction

Cost-effective fabrication of mechanically flexible low-power electronics is important for emerging applications including wearable electronics, artificial intelligence, and the Internet of Things. Here, solution-processed source-gated transistors (SGTs) with an unprecedented intrinsic gain of ~2,000, low saturation voltage of +0.8 ± 0.1 V, and a ~25.6 μW power consumption are realized using an indium oxide In2O3/In2O3:polyethylenimine (PEI) blend homojunction with Au contacts on Si/SiO2. Kelvin probe force microscopy confirms source-controlled operation of the SGT and reveals that PEI doping leads to more effective depletion of the reverse-biased Schottky contact source region. Furthermore, using a fluoride-doped AlOx gate dielectric, rigid (on a Si substrate) and flexible (on a polyimide substrate) SGTs were fabricated. These devices exhibit a low driving voltage of +2 V and power consumption of ~11.5 μW, yielding inverters with an outstanding voltage gain of >5,000. Furthermore, electrooculographic (EOG) signal monitoring can now be demonstrated using an SGT inverter, where a ~1.0 mV EOG signal is amplified to over 300 mV, indicating significant potential for applications in wearable medical sensing and human-computer interfacing.

Sub-9 nm high-performance and low-power transistors based on an in-plane NbSe2/MoSe2/NbSe2 heterojunction.

Due to the ability to reduce the gate length of field-effect transistors (FETs) down to sub-10 nm without obviously affecting the performance of the device, the utilization of two-dimensional (2D) semiconductor materials as channel materials for FETs is of great interest. However, in-plane 2D/2D heterojunction FETs have received less attention in previous studies than vertical van der Waals heterojunction devices. Based on the above reasons, this study has investigated the transport properties of an in-plane NbSe2/MoSe2/NbSe2 heterojunction FET with different gate lengths by using ab initio quantum transport simulation. The results reveal that a gate length of sub-9 nm gives the device a low subthreshold swing down to 62 mV dec-1 and a high on-state current up to 1040 μA μm-1. Most importantly, the on-state current, delay time, and power dissipation of the FET with the optimized channel length can nearly meet or even exceed the high-performance and low-power requirements of the International Technology Roadmap for Semiconductors. The findings for this FET can provide the design and development guidance for other in-plane heterojunction electrical devices in the post-Moore era.

Wirelessly powered large-area electronics for the Internet of Things

Powering the increasing number of sensor nodes used in the Internet of Things creates a technological challenge. The economic and sustainability issues of battery-powered devices mean that wirelessly powered operation—combined with environmentally friendly circuit technologies—will be needed. Large-area electronics—which can be based on organic semiconductors, amorphous metal oxide semiconductors, semiconducting carbon nanotubes and two-dimensional semiconductors—could provide a solution. Here we examine the potential of large-area electronics technology in the development of sustainable, wirelessly powered Internet of Things sensor nodes. We provide a system-level analysis of wirelessly powered sensor nodes, identifying the constraints faced by such devices and highlighting promising architectures and design approaches. We then explore the use of large-area electronics technology in wirelessly powered Internet of Things sensor nodes, with a focus on low-power transistor circuits for digital processing and signal amplification, as well as high-speed diodes and printed antennas for data communication and radiofrequency energy harvesting.

Multivalley Electron Conduction at the Indirect-Direct Crossover Point in Highly Tensile-Strained Germanium

For applications such as low-power tunneling transistors and memory, lasers, qubits, and spintronics, there is interest in using strain to enhance carrier mobility in semiconductors. This experimental and theoretical study investigates transport in highly strained germanium, in which multivalley electron conduction emerges. Surprisingly, all conduction occurs via the L valley in Ge for biaxial tensile strain below 1.6%, while above the contribution from the \ensuremath{\Gamma} valley increases, with negligible contributions from the underlying strain template.

(Digital Presentation) Nanowire Transistors with Bound‐Charge Engineering

Low-dimensional electronic systems such as silicon nanowires exhibit weak screening which is detrimental to the performance and scalability of nanodevices, e.g., tunnel field-effect transistors. By atomistic quantum transport simulations, we show how bound charges can be engineered at interfaces of Si and low-κ oxides to strengthen screening. To avoid compromising gate control, low-κ and high-κ oxides areused in conjunction. In Si nanowire tunnel field-effect transistors, we demonstrate that bound charge engineering increases the on-state current by orders of magnitude, and the combination of oxides yields minimal subthreshold swing. Finally, an analytical model is developed for Si nanowire FET assisted by bound charge engineering. We conclude that the proposed bound-charge engineering paves a way toward improved low-power transistors.

Evolution Application of Two-Dimensional MoS2-Based Field-Effect Transistors

High-performance and low-power field-effect transistors (FETs) are the basis of integrated circuit fields, which undoubtedly require researchers to find better film channel layer materials and improve device structure technology. MoS2 has recently shown a special two-dimensional (2D) structure and superior photoelectric performance, and it has shown new potential for next-generation electronics. However, the natural atomic layer thickness and large specific surface area of MoS2 make the contact interface and dielectric interface have a great influence on the performance of MoS2 FET. Thus, we focus on its main performance improvement strategies, including optimizing the contact behavior, regulating the conductive channel, and rationalizing the dielectric layer. On this basis, we summarize the applications of 2D MoS2 FETs in key and emerging fields, specifically involving logic, RF circuits, optoelectronic devices, biosensors, piezoelectric devices, and synaptic transistors. As a whole, we discuss the state-of-the-art, key merits, and limitations of each of these 2D MoS2-based FET systems, and prospects in the future.