Low-power Transimpedance Amplifier Research Articles

80 dB tuning range transimpedance amplifier exploiting the Switched-Resistor approach

This paper presents the design of a low-noise, low-power transimpedance amplifier (TIA) for biomedical applications. The proposed TIA exploits for the first time in the literature a Switched–Resistor (SR) as the feedback element in order to achieve a digitally tunable transimpedance gain with an extremely large tuning range (higher than 80 dB) and a maximum value as high as 10 GΩ. Another important feature which comes with the adoption of the SR technique is that the output voltage is already sampled with the SR clock signal and this simplifies the design of the following digitizer block. The circuit has been designed in a commercial 130 nm CMOS technology and simulation results show a minimum IRCSN (input-referred current spectrum noise) of 1.67 fA/√Hz and a total power consumption of 0.9 μW with a 0.6 V supply voltage. Extensive parametric and Monte Carlo simulations have confirmed a good robustness against PVT and mismatch variations.

Low input-resistance low-power transimpedance amplifier design for biomedical applications

This paper introduces a Transimpedance Amplifier (TIA) design capable of producing an incremental input resistance in the ohmic range, for input signals in the microampere range, such as are encountered in the design of instrumentation for electrochemical ampero-metric sensors, optical-sensing and current-mode circuits. This low input-resistance is achieved using an input stage incorporating negative feedback. In a Cadence simulation of an exemplary design using a 180 nm CMOS process and operating with ± 1.8 V supply rails, the input resistance is 1.05 ohms and the power dissipation is 93.6 µW. The bandwidth, for a gain of 100 dBohm, exceeded 9 MHz. For a 1µA, 1 MHz sinusoidal input signal the Total Harmonic Distortion, with this gain, is less than 1%. The input referred noise current with zero photodiode capacitance is 2.09 pA/√Hz and with a photodiode capacitance of 2pF is 8.52 pA/√Hz. Graphical data is presented to show the effect of a photodiode capacitance varying from 0.5 to 2 pF, when the TIA is used in optical sensing. In summary, the required very low input resistance, at a low input current level (µA) is achieved and furthermore a Table is included comparing the characteristics and a widely used Figure of Merit (FOM) for the proposed TIA and similar published low-power TIAs. It is apparent from the Table that the FOM of the proposed TIA is better than the FOMs of the other TIAs mentioned.

A 40-Gb/s, 900-fJ/bit Dual-Channel Receiver in a 45-nm Monolithic RF/Photonic Integrated Circuit Process

An energy-efficient dual-channel receiver (RX) for short range optical interconnects is integrated in a 45-nm RF/photonic process and characterized for electrical bandwidth to de-embed the photonic device limitations. Each channel receiver consists of a low-power transimpedance amplifier (TIA), limiting amplifier (LA), and output buffer (OB) which is implemented with minimal area footprint using active gyrators and feedforward capacitive compensation for bandwidth enhancement and only a single pair of inductors on the OB. The electrical characterization includes the data rate and bit error rate (BER) to 40 Gb/s per channel. The total energy efficiency is 0.9 pJ/bit including the output buffer and 0.36 pJ/bit excluding the OB at a data rate of 40 Gb/s per channel.

A Multi-Stage TIA based on Cascoded-Inverter Structures for Low-power Applications

This article discusses a multi-stage transimpedance amplifier (TIA), which is based on three stages of a modified inverter structure. The traditional inverter structures’ performances are improved adding two cascoded transistors. This new structure benefits from elimination of the Miller-capacitances in comparison with the traditional inverters, which can provide higher speed and wider frequency bandwidth. Manipulating the trade-offs among bandwidth, gain and power consumption beside using Gm/ID technique, this paper introduces a low-power transimpedance amplifier for high-bit rates in optical communication receiver systems. Moreover, active types of inductors are also used to lesson the occupied area and increase the frequency bandwidth. Transferring poles of the improved circuit to higher frequencies means less required DC current for a fixed bandwidth range, which results in low-power characteristic.

Low-power transimpedance amplifier for cryogenic integration with quantum devices

The development of quantum electronic devices operating below a few Kelvin degrees is raising the demand for cryogenic complementary metal-oxide-semiconductor electronics (CMOS) to be used as in situ classical control/readout circuitry. Having a minimal spatial separation between quantum and classical hardware is necessary to limit the electrical wiring to room temperature and the associated heat load and parasitic capacitances. Here, we report prototypical demonstrations of hybrid circuits combining silicon quantum dot devices and a classical transimpedance amplifier, which is characterized and then used to measure the current through the quantum dots. The two devices are positioned next to each other at 4.2 K to assess the use of the cryogenic transimpedance amplifier with respect to a room-temperature transimpedance amplifier. A quantum device built on the same substrate as the transimpedance amplifier is characterized down to 10 mK. The transimpedance amplifier is based on commercial 28 nm fully depleted Silicon-on-insulator (FDSOI) CMOS. It consists of a two-stage Miller-compensated operational amplifier with a 10 MΩ polysilicon feedback resistor, yielding a gain of 1.1×107 V/A. We show that the transimpedance amplifier operates at 10 mK with only 1 μW of power consumption, low enough to prevent heating. It exhibits linear response up to ±40 nA and a measurement bandwidth of 2.6 kHz, which could be extended to about 200 kHz by design optimization. The realization of custom-made electronics in FDSOI technology for cryogenic operation at any temperature will improve measurement speed and quality inside cryostats with higher bandwidth, lower noise, and higher signal-to-noise ratio.

Design of an Inverter-Base, Active-Feedback, Low-Power Transimpedance Amplifier Operating at 10 Gbps

In this paper, a low-power structure as an inverter-base circuit is reported for broadband applications. The focus in this study is in obtaining a low-power structure. By applying cascoded structure to an inverter as a feedforward network in the structure, the DC current and hence the power dissipation are decreased. Also, by adding a two-stage active feedback, which yields no miller capacitance, to the cascoded inverter, the structure of the TIA is completed. Simulation results in HSPICE using 90[Formula: see text]nm CMOS technology parameters show 41[Formula: see text]dB[Formula: see text] transimpedance gain, 6.5[Formula: see text]GHz frequency bandwidth and 2.7[Formula: see text][Formula: see text]Arms input referred noise, which consumes only 1.67[Formula: see text]mw power at 1[Formula: see text]V supply. Results and analysis indicate that the proposed TIA is suitable to work as a low-power 10 Gbps transimpedance amplifier in an optical receiver.

A low-power low-noise multi-stage transimpedance amplifier for amperometric based blood glucose monitoring systems

In this paper, the design of low-noise, low-power transimpedance amplifier (TIA) is presented for a miniaturized amperometric based continuous blood glucose monitoring system for wearable devices. The proposed multi-stage cascode common source transimpedance amplifier circuit is designed and implemented in a 180 nm CMOS technology. It has been demonstrated that the proposed TIA shows a significant increase in transimpedance gain, 1.72 GΩ with a bandwidth of 180 kHz and input referred current noise is 18 fA/√Hz for an input current of 200 pA. The total power consumption is 52 μW with a 1.4 V supply and occupies a chip area of 110 μm × 140 μm.

A RGC-based, low-power, CMOS transimpedance amplifier for 10Gb/s optical receivers

ABSTRACTIn this paper, a new low-power transimpedance amplifier (TIA) based on a modified Regulated Cascode (RGC) circuit structure followed by a closed-loop post-amplifier is proposed for 10 Gb/s applications. The main objective of this work is to reduce the power consumption while, the frequency bandwidth of the proposed amplifier is increased considerably. The booster of a conventional RGC is modified by a cascoded transistor and its effect on the performance of the circuit is studied mathematically, which are verified by simulations. The bandwidth extension is occurred due to increasing the gain of the booster amplifier in the RGC stage, which isolates further the input capacitance and results in a reduced input resistance value hence, a higher input pole frequency is obtained in comparison with other conventional RGC structures. On the other hand, by using an active inductive peaking technique, the frequency of the output pole is also increased which results in a further extension of the frequency bandwidth for the proposed circuit. The proposed TIA is simulated using 90 nm CMOS technology parameters, which shows a 50.5 dBΩ transimpedance gain, 7.3 GHz frequency bandwidth and 1.22 µArms input referred noise value for only 1 mW of power consumption at 1.2 V supply voltage.

40-Gb/s PAM-4 Transmission Over a 40 km Amplifier-Less Link Using a Sub-5V Ge APD

Avalanche photodetectors (APDs) integrated in a silicon platform have the potential to significantly improve the link budget of optical links compared with conventional p-i-n photodetectors, while only requiring CMOS-friendly biasing voltages. We demonstrate an optical receiver based on a 1310nm <5V Germanium APD and a low-power transimpedance amplifier that offers a 5 to 6 dB sensitivity improvement compared with operation in PIN-mode. Sub-FEC transmission using PAM-4 in an amplifier-less link over more than 42km at 40Gb/s and over 10 km at 50 Gb/s is shown with a commercial directly modulated laser as transmitter.

A CMOS lock-in amplifier for low-power biomedical applications

An analogue Lock-In Amplifier (LIA) is employed in an optical receiver front end to retrieve signals from an extremely noisy environment. The conventional LIA consists of a current source, Transimpedance Amplifier (TIA), set of active Gm-C filter and Phase Locked Loop (PLL). In this work, a high gain low power TIA making use of Operational Transconductance Amplifier (OTA) is proposed. This structure has a 54% improvement in gain and consumes 8% lesser power compared to replica biasing TIA. The gain boosting circuit in the NMOS current steering charge pump reduces the power consumption by 38% compared to conventional structure. In the modified Phase Frequency Detector (PFD), True Single Phase Clock (TSPC) logic is utilised which consumes 50% lesser power compared to conventional design. So, the low power LIA designed with proposed structures can be used for low power biomedical applications. Simulations are done using Cadence Spectre, GPDK 180 nm technology.

A 40-Gb/s Transimpedance Amplifier for Optical Links

This letter presents a low-power transimpedance amplifier (TIA), supporting both 25 and 40-Gb/s communication. It exhibits an optical modulation amplitude sensitivity of −10.6 dBm at 25 Gb/s and −6.4 dBm at 40 Gb/s using a photodiode with a responsivity of 0.55 A/W. The TIA consumes 158 mW from a 2.5 V supply and was manufactured in a 0.13- $\mu \text{m}$ SiGe BiCMOS process. Compared with the state of the art, the presented TIA exhibits a similar sensitivity (at both 25 and 40 Gb/s), while exhibiting a low power consumption for the 40-Gb/s operation.

A CMOS Low-Power Cross-Coupled Immittance-Converter Transimpedance Amplifier

This letter presents a low-power transimpedance amplifier (TIA) that employs an immittance converter, which provides both a negative input resistance to increase the input pole frequency and a negative inductance to improve the circuit stability. These allow for a significant bandwidth enhancement with low power consumption. Two TIAs, TIA1 with 6 GHz and TIA2 with 8.8 GHz 3 dB bandwidths, were fabricated in a standard 0.13- μm CMOS technology and were designed to operate with a 250 fF photodiode capacitance at 10 Gb/s. The transimpedance gains of the single-stage TIAs, followed by near-unity-gain output-matching buffers, are ~ 54 dBΩ, the group-delay variations and average input-referred noise currents are ±3 ps and 24 pA/√{Hz} (TIA1) and ±70 ps and 28 pA/√{Hz} (TIA2) over their 3 dB bandwidths. The TIAs occupy an active area of 250 μm× 160 μm, and without the output-matching buffer each consumes 2 mW.

A 6 Gb/s Low Power Transimpedance Amplifier with Inductor Peaking and Gain Control for 4-channel Passive Optical Network in 0.13 μm CMOS

This paper presents a 6 Gb/s 4-channel arrayed transimpedance amplifiers (TIA) with the gain control for 4-channel passive optical network in 0.13 ㎜ complementary metal oxide semiconductor (CMOS) technology. A regulated cascode input stage and inductive-series peaking are proposed in order to increase the bandwidth. Also, a variable gain control is implemented to provide flexibility to the overall system. The TIA has a maximum 98.1 ㏈Ω gain and an input current noise level of about 37.8 ㎀/㎐. The die area of the fabricated TIA is 1.9 ㎜ x 2.2 ㎜ for 4-channel. The power dissipation is 47.64 ㎽/1ch.

CMOS VLSI Potentiostat for Portable Environmental Sensing Applications

This paper reports an integrated CMOS potentiostat for detection of heavy metal ions in water and other solvents based on electrochemical sensing. The proposed potentiostat features a low-input impedance, high sensitivity, high gain and low power transimpedance amplifier front end, with programmable control of electrode potential, thus facilitating continuous bidirectional measurement of reduction-oxidation (redox) current in a potentiostat for cyclic voltammetry (CV) experiment. For proof of concept, we use the proposed integrated potentiostat to perform CV on a reference ferricyanide (K3Fe(CN)6) using external microelectrodes. Results compared with standard benchtop potentiostat confirm microelectrode behavior with accurate estimate of redox potential with varying redox currents proportional to the ferricyanide concentration.

High-Performance BiCMOS Transimpedance Amplifiers for Fiber-Optic Receivers

High gain, wide bandwidth, low noise, and low-power transimpedance amplifiers based on new BiCMOS common- base topologies have been designed for fiber-optic receivers. In particular a design approach, hereafter called "A more- FET approach", added a new dimension to effectively optimize performance tradeoffs inherent in such circuits. Using conventional silicon 0.8 μm process parameters, simulated performance features of a total-FET transimpedance amplifier operating at 7.2 GHz, which is close to the technology fT of 12 GHz, are presented. The results are superior to those of similar recent designs and comparable to IC designs using GaAs technology. A detailed analysis of the design architecture, including a discussion on the effects of moving toward more FET-based designs is presented.

A BiCMOS 120 mW 11 GHz TRANSIMPEDANCE AMPLIFIER DEDICATED FOR HIGH-SPEED PHOTORECEIVERS

We present a new low-noise, low-power SiGe transimpedance amplifier (TIA) by combining an automatic DC photo-current cancellation, an on-chip DC offset compensation circuit and a single-ended to differential conversion scheme. The conversion method is based of the replica biasing technique in order to provide balanced output signals to the subsequent stages. The chip was fabricated in a 0.18 μm SiGe BiCMOS technology. Experimental results show excellent performances such as 11 GHz bandwidth, 75-dBΩ transimpedance, -19.2 dBm sensitivity measured at 10 Gb/s at a Bit Error Rate (BER) of 10-12, [Formula: see text] input referred noise, and 9.5 ps peak-to-peak jitter which are the best overall performances reported in its category. The photoreceiver chip is expected to dissipate only 120 mW from a single 3.3 V power supply.

Monolithically integrated CMOS current-mode transimpedance preamplifier

A wideband low-power current-mode transimpedance amplifier has been designed and implemented in 0.18 µm standard digital CMOS technology. Current shunt feedback technology is used to provide low input impedance and broaden the bandwidth. This current-mode common gate preamplifier has a transimpedance 60 dB Ω with a bandwidth of 3.2 GHz, and can operate at 5 Gbit/s with large dynamic range.