Low-power Solution Research Articles

Research on the Scrambling and De-scrambling Technique of Pseudorandom Sequences Based on Linear Feedback Shift Register

With the rapid development of communication technology, the security and reliability of signal transmission and antiinterference ability have become a key challenge. Aiming at the problems, this paper deeply studies the scrambling and de-scrambling technique of pseudo-random sequences, and designed the corresponding circuit to better understand the working mode of each step. In this study, the design and implementation of the scrambling and de-scrambling technique of pseudo-random sequences circuit is carried out through Verilog language, and the advantages and disadvantages of the designed circuit are analyzed in detail and the improvement scheme is obtained. In addition, this study also compares and analyzes the advantages and disadvantages of the scrambling and de-scrambling technique of pseudorandom sequences and the scrambling and de-scrambling technique of self-synchronizing, which provides a reliable basis for selecting appropriate technical solutions in practical application scenarios. This study provides theoretical support and reference for the design of communication systems, and looks forward to the future development direction of the scrambling technology, including the development of more efficient algorithms, the exploration of adaptive techniques, and the development of low-power solutions.

FloatingBlue: A Delay Tolerant Networks-Enabled Internet of Things Architecture for Remote Areas Combining Data Mules and Low Power Communications.

Monitoring vast and remote areas like forests using Wireless Sensor Networks (WSNs) presents significant challenges, such as limited energy resources and signal attenuation over long distances due to natural obstacles. Traditional solutions often require extensive infrastructure, which is impractical in such environments. To address these limitations, we introduce the "FloatingBlue" architecture. This architecture, known for its superior energy efficiency, combines Bluetooth Low Energy (BLE) technology with Delay Tolerant Networks (DTN) and data mules. It leverages BLE's low power consumption for energy-efficient sensor broadcasts while utilizing DTN-enabled data mules to collect data from dispersed sensors without constant network connectivity. Deployed in a remote agricultural area in the Amazon region, "FloatingBlue" demonstrated significant improvements in energy efficiency and communication range, with a high Packet Delivery Ratio (PDR). The developed BLE beacon sensor achieved state-of-the-art energy consumption levels, using only 2.25 µJ in sleep mode and 11.8 µJ in transmission mode. Our results highlight "FloatingBlue" as a robust, low-power solution for remote monitoring in challenging environments, offering an energy-efficient and scalable alternative to traditional WSN approaches.

High-Resolution and Robust One-Bit Direct-of-Arrival Estimation via Reweighted Atomic Norm Estimation.

In recent years, one-bit quantization has attracted widespread attention in the field of direction-of-arrival (DOA) estimation as a low-cost and low-power solution. Many researchers have proposed various estimation algorithms for one-bit DOA estimation, among which atomic norm minimization algorithms exhibit particularly attractive performance as gridless estimation algorithms. However, current one-bit DOA algorithms with atomic norm minimization typically rely on approximating the trace function, which is not the optimal approximation and introduces errors, along with resolution limitations. To date, there have been few studies on how to enhance resolution under the framework of one-bit DOA estimation. This paper aims to improve the resolution constraints of one-bit DOA estimation. The log-det heuristic is applied to approximate and solve the atomic norm minimization problem. In particular, a reweighted binary atomic norm minimization with noise assumption constraints is proposed to achieve high-resolution and robust one-bit DOA estimation. Finally, the alternating direction method of multipliers algorithm is employed to solve the established optimization problem. Simulations are conducted to demonstrate that the proposed algorithm can effectively enhance the resolution.

Maximizing the IRS’s Gains in NLOS Communication through Optimal Positioning

Background: Recently, an IRS has been proposed as a low-cost and effective solution for performance improvement in wireless communication. However, the configuration and setup necessary to derive optimal results have not been identified yet. Objective: The paper seeks to build the knowledge by investigating the effects of IRS in the LOS and NLOS environment to verify the achievable gains from each and examine how different IRS positions impact the BER. Methods: An IRS model was simulated in MATLAB to investigate the channel capacity gain of an IRS in LOS and NLOS scenarios for the verification of performance gains. Further, the effects of the IRS positioning (with respect to transmitter and end-user) on the BER were investigated. Results: The channel capacity of an IRS system was found to be lower by 12Mbps compared to that of a direct link in a LOS scenario. This demonstrates that a passive IRS is only beneficial in the absence of a line of sight. In the case of a NLOS, for an SNR of 50, MIMO transmitter diversity and receiver diversity had channel capacities of 1.0 Mbps and 4.5 Mbps, respectively while the IRS system achieved 22 Mbps. As such, it is more beneficial to create an alternative path via the IRS than to increase the number of transmit or receive antennas. The positioning of the IRS had a significant impact on the BER. From the results, positioning the IRS mid-way between the AP and STA led to up to 57.69% improvements in BER compared to close to STA or close to AP arrangements. Conclusion: The results prove that an IRS is a cost-effective, low-power consumption solution for overcoming challenges associated with NLOS communication. The work also identified the ideal positioning of the IRS to be the midpoint between AP and STA, for the WLAN system. Further research will be needed to verify performance in other systems.

When in-memory computing meets spiking neural networks—A perspective on device-circuit-system-and-algorithm co-design

This review explores the intersection of bio-plausible artificial intelligence in the form of spiking neural networks (SNNs) with the analog in-memory computing (IMC) domain, highlighting their collective potential for low-power edge computing environments. Through detailed investigation at the device, circuit, and system levels, we highlight the pivotal synergies between SNNs and IMC architectures. Additionally, we emphasize the critical need for comprehensive system-level analyses, considering the inter-dependencies among algorithms, devices, circuit, and system parameters, crucial for optimal performance. An in-depth analysis leads to the identification of key system-level bottlenecks arising from device limitations, which can be addressed using SNN-specific algorithm–hardware co-design techniques. This review underscores the imperative for holistic device to system design-space co-exploration, highlighting the critical aspects of hardware and algorithm research endeavors for low-power neuromorphic solutions.

Standalone edge AI-based solution for Tomato diseases detection

Tomato yield is significantly affected by diseases, which are a continuous challenge for its production and pose threats to its global supply chain. Automatic and early detection of these diseases could help growers to swiftly adopt mitigation strategies to limit the disease spread, leading to improved production. Deep learning-based CNN approaches have been widely applied to detect tomato diseases. However, deep learning models are highly computationally demanding, resulting in a computational bottleneck for practical adaptation for agricultural applications such as disease detection and monitoring. Over the last few years, developments of open-source Edge systems have provided opportunities for low-cost and low-power consumption practical solutions for deep learning applications for agriculture. Therefore, the primary goal of this study was to evaluate the performance of standalone Edge-AI solutions for tomato leaf disease detection. To achieve this goal, firstly, this study employed lightweight deep learning networks to detect and differentiate tomato leaf diseases (bacterial spot, early blight, healthy, late blight, leaf mold, septoria leaf spot, two spotted spider mites, target spot, and yellow leaf curl virus). Then, these deep learning networks were deployed on low-cost and low-power consumption Edge devices to investigate their performance capabilities as standalone Edge-AI solutions for the early detection of tomato leaf diseases. Lightweight CNN based GoogleNet and MobileNetV2 deep learning networks achieved accuracies of up to 98.25 % compared to accuracies of 98.13 %, 98.13 %, 94.62 %, and 90.67 % of EfficientNetB0, ResNet-18, SqueezeNet, and NasNetMobile, respectively, in detecting tomato diseases. NVIDIA Jetson ORIN AGX and Nano significantly outperformed Raspberry Pi and Raspberry Pi with AI accelerator (Google Coral) in image classification, achieving classification times of 3.5 ms and 5.2 ms respectively, using SqueezeNet, compared to 15.3 ms and 10.5 ms on the Raspberry Pi devices. In addition, Raspberry Pi with Google Coral achieved the best cost/FPS performance of 0.14 compared to other Edge devices NVIDIA Jetson AGX Orin and NVIDIA Jetson Nano Orin with cost/FPS of 0.7 and 0.26, respectively. These results showed the potential of standalone Edge-AI solutions using low-cost and low-power consuming software and hardware resources for early tomato disease detections.

Low-Cost, Low-Power Edge Computing System for Structural Health Monitoring in an IoT Framework.

A complete low-power, low-cost and wireless solution for bridge structural health monitoring is presented. This work includes monitoring nodes with modular hardware design and low power consumption based on a control and resource management board called CoreBoard, and a specific board for sensorization called SensorBoard is presented. The firmware is presented as a design of FreeRTOS parallelised tasks that carry out the management of the hardware resources and implement the Random Decrement Technique to minimize the amount of data to be transmitted over the NB-IoT network in a secure way. The presented solution is validated through the characterization of its energy consumption, which guarantees an autonomy higher than 10 years with a daily 8 min monitoring periodicity, and two deployments in a pilot laboratory structure and the Eduardo Torroja bridge in Posadas (Córdoba, Spain). The results are compared with two different calibrated commercial systems, obtaining an error lower than 1.72% in modal analysis frequencies. The architecture and the results obtained place the presented design as a new solution in the state of the art and, thanks to its autonomy, low cost and the graphical device management interface presented, allow its deployment and integration in the current IoT paradigm.

A 0.5 V, 32 nW Compact Inverter-Based All-Filtering Response Modes Gm-C Filter for Bio-Signal Processing

A low-power, low-voltage universal multi-mode Gm-C filter using a 180 nm TSMC technology node is presented in this paper. The proposed filter employs only three transconductance operational amplifiers (OTAs) operating in the sub-threshold region with a supply voltage of 0.5 V, resulting in a power consumption of 32 nW. Moreover, without additional active elements, the proposed circuit can operate various functional modes, such as voltage, current, transconductance, and trans-resistance. The filter’s frequency, centered at 462 Hz, and a compact and low-power solution showing only 93.5 µVrms input-referred noise make the proposed filter highly suitable for bio-signal processing.

Benchmarking analysis of computer vision algorithms on edge devices for the real-time detection of digital dermatitis in dairy cows

Digital dermatitis (DD) is a bovine claw disease responsible for ulcerative lesions on the coronary band of the foot. It causes significant animal welfare and economic losses to the cattle industry. Early detection of DD can lead to prompt treatment and decrease lameness. Current detection and staging methods require a trained individual to evaluate the interdigital space on each foot for clinical signs of DD. Computer vision (CV), a type of artificial intelligence for image analysis, has demonstrated promising results on object detection tasks. However, farms require robust solutions that can be deployed in harsh conditions including dust, debris, humidity, precipitation, other equipment issues. The study aims to train, deploy, and benchmark DD detection models on edge devices. Images were collected from commercial dairy farms with the camera facing the interdigital space on the plantar surface of the foot. Images were scored for M-stages of DD by a trained investigator using the M-stage DD classification system. Models were trained to detect and score DD lesions and embedded on an edge device. The Tiny YOLOv4 model deployed on a CV specific integrated camera module connected to a single board computer achieved a mean average precision (mAP) of 0.895, an overall prediction accuracy of 0.873, and a Cohen’s kappa of 0.830 for agreement between the computer vision model and the trained investigator. The model reached a final inference speed of 40 frames per second (FPS) and ran stably without any interruptions. The CV model was able to detect DD lesions on an edge device with high performance and speed. The CV tool can be used for early detection and prompt treatment of DD in dairy cows. Real-time detection of DD on edge device will improve health outcomes, while simultaneously decreasing labor costs. We demonstrate that the deployed model can be a low-power and portable solution for real-time detection of DD on dairy farms. This result is a step towards applying CV algorithms to veterinary medicine and implementing real-time detection of health outcomes in precision farming.

Enhancing Sustainable Transportation with Advancements in Photonic Radar Technology with MIMO and IIR Filtering for Adverse Weather Conditions

Sustainable transportation is crucial in addressing global road safety and environmental challenges. This study introduces a novel photonic radar system, leveraging Linear Frequency-Modulated Continuous Wave (LFMCW) technology for high-speed data transmission. Operating in a homodyne configuration, this system uses a single oscillator to generate both signal and reference waveforms. It incorporates mode division multiplexing (MDM) to enable the detection and ranging of multiple targets, even under adverse atmospheric conditions. To counter atmospheric attenuation, the system is equipped with a 2 × 2 MIMO technique and an Infinite Impulse Response (IIR) filter. Numerical simulations demonstrate the system’s superior performance in range resolution and target detection, achieving significant power improvements. The IIR filter further enhances detection, achieving a power improvement of 200% for target 1 and 276% for target 2. With low power requirements and enhancement through IIR filter equalization, this system presents a viable option for battery-operated vehicles. This innovative approach offers a low-power high-efficiency solution suitable for battery-operated vehicles, promoting safer and more reliable sustainable transportation.

LENet: Lightweight and Effective Detector for Aerial Object

Aerial object detection is crucial in various computer vision tasks, including video monitoring, early warning systems, and visual tracking. While current methods can accurately detect normal-sized objects, they face challenges distinguishing small objects from cluttered backgrounds. Developing methods that can be deployed on edge devices to achieve fast, accurate, and energy-efficient performance is also an urgent challenge. This paper proposes a network for aerial object detection by incorporating an attention mechanism to enhance feature extraction and elevate the accuracy of aerial moving object detection. Additionally, we optimize the channel dimensions of the feature extraction framework, resulting in a reduction in model parameters, acceleration of inference speed, and alleviation of the computational burden. Ulteriorly, we optimize the Spatial Pyramid Pooling (SPP) module to enhance detection accuracy and processing speed. Inspired by the ResNet and RepVGG structures, we design a feature fusion module to combine early-extracted features, improving speed and accuracy. Based on the design mentioned above principles, we develop a neural network method with an impressively small model size of only [Formula: see text][Formula: see text]M. The proposed approach achieves state-of-the-art performance on five benchmark datasets. Besides its superior performance, our method demonstrates excellent throughput on edge computing devices. Experimental results show that even when running on low-performance computing devices, the CPU and GPU temperatures remain below 50∘C and achieve a detection speed of 14.8 frames per second (fps) and power consumption of only 2.9[Formula: see text]W. These findings suggest that a high-accuracy, low-power, low-latency, and low-memory footprint aerial object detection solution is achievable.

Low Power Design of Efficient Wireless Sensor Node

Abstract: The escalating demand for rapid, efficient System on Chip (SoC) designs has intensified the need for low-power solutions, particularly in Wireless Sensor Nodes reliant on battery power. This research centers on leveraging clock gating to curtail dynamic power usage in an 8-bit Arithmetic and Logic Unit (ALU). Employing the Hans-Carlson Adder for addition and a 4x4 approximation multiplier, the ALU processes data from a humidity sensor module. Simulations using Xilinx Vivado reveal a substantial 65–73% reduction in power consumption at higher frequencies. This ALU, adept at minimizing power, emerges as a viable processing element for energy-sensitive sensor node applications, ensuring prolonged operational longevity.

Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

Reversible Logic Gates and Applications – A Low Power Solution to VLSI Chips

Leveraging Bit-Serial Architectures for Hardware-Oriented Deep Learning Accelerators with Column-Buffering Dataflow

Bit-serial neural network accelerators address the growing need for compact and energy-efficient deep learning tools. Traditional neural network accelerators, while effective, often grapple with issues of size, power consumption, and versatility in handling a variety of computational tasks. To counter these challenges, this paper introduces an approach that hinges on the integration of bit-serial processing with advanced dataflow techniques and architectural optimizations. Central to this approach is a column-buffering (CB) dataflow, which significantly reduces access and movement requirements for the input feature map (IFM), thereby enhancing efficiency. Moreover, a simplified quantization process effectively eliminates biases, streamlining the overall computation process. Furthermore, this paper presents a meticulously designed LeNet-5 accelerator leveraging a convolutional layer processing element array (CL PEA) architecture incorporating an improved bit-serial multiply–accumulate unit (MAC). Empirically, our work demonstrates superior performance in terms of frequency, chip area, and power consumption compared to current state-of-the-art ASIC designs. Specifically, our design utilizes fewer hardware resources to implement a complete accelerator, achieving a high performance of 7.87 GOPS on a Xilinx Kintex-7 FPGA with a brief processing time of 284.13 μs. The results affirm that our design is exceptionally suited for applications requiring compact, low-power, and real-time solutions.

A 0.59 nW/kHz Clock Circuit with High-Precision Clock Calibration for Passive Internet of Things Chips

The high precision and low power consumption of the clock generator are critical in passive RFID transponders and passive IoT chips, but fluctuations in PVT can cause considerable degradation in the precision of the chip’s internal clocks. This paper proposes a high-precision clock circuit with a single-shot calibration method to addresses this issue in a low-power clock solution. Based on the reference timespan in the preamble of the down-link RF envelope, a TDIF (Time-digital to current-frequency) calibration method was implemented with both a streamlined procedure and customized circuits. By computing the difference between the time counts and applying it to an ultra-low-power, current-starved oscillator, the current change ratio can be linearly controlled. Compared to the traditional integer frequency division scheme used by passive tags for a 160 k bits up-link data rate, the required frequency for the clock generator was reduced from 960 kHz to 320 kHz, the calibration error was reduced from ±10% to ±3% for ±25% frequency deviation, the calibration time was 133.3 μs for a single shot in this work, and the power consumption was 158 nW after the calibration was completed. This leads to an excellent power efficiency of 0.59 nW/kHz and meets the requirements of low power, low cost, and PVT robustness in the RF-powered passive IoT chips. By appropriately increasing the number of calibration digits and the duration, this calibration approach could also be used for other ultra-low-power passive IoT chips that require higher-precision clocking without the use of off-chip crystals.

The synthesis method of series-based bistable compliant mechanisms for rigid-body guidance problem based on geometrical similarity transformation of pole maps

Abstract Designing guidance mechanisms using bistable mechanisms with two stable positions is a common low-power solution for maintaining the guidance position without continuous external energy input. However, the coupling between kinematics and statics in compliant bistable mechanisms poses a challenge for their application in mechanism synthesis. To address this issue, this paper introduces the pole similarity transformation theory into the synthesis of compliant mechanisms and proposes a general synthesis method for planar serial-based compliant bistable mechanisms. This method models the compliant mechanism using the strain energy method and analyzes the bistable characteristics of the mechanism within its motion plane using the saddle point searching method. By doing so, the proposed method can identify stable positions without predetermined motion trajectories, making it more suitable for designing compliant bistable mechanisms with general planar motion. Additionally, this method utilizes the pole map to describe the stable positions of the rigid components in the compliant mechanism and establishes an information database for compliant bistable mechanisms. Through leveraging the pole similarity transformation, the pole maps of the mechanisms in the information database are matched with the pole map of the motion task, thus achieving the synthesis of planar serial-based compliant bistable mechanisms for the rigid-body guidance problem. The paper provides a detailed explanation of the mechanism synthesis process and demonstrates its application through a case study.

Integrated liquid-crystal-based variable-tap devices for visible-light amplitude modulation.

In this Letter, we propose and experimentally demonstrate the first, to our knowledge, integrated liquid-crystal-based (LC-based) variable-tap devices for visible-light amplitude modulation. These devices leverage the birefringence of LC medium to actively tune the coupling coefficient between two waveguides. First, we develop the device structure, theory of operation, and design procedure. Next, we summarize the fabrication and LC packaging procedure for these devices. Finally, we experimentally demonstrate amplitude modulation with 15.4-dB tap-port extinction within ±3.1 V for a 14-µm-long device at a 637-nm operating wavelength. These small-form-factor variable-tap devices provide a compact and low-power solution to integrated visible-light amplitude modulation and will enable future high-density integrated visible-light systems.

Evaluation of Assembler and C Programming Languages on PIC16F877 Microcontroller

The programming of microcontrollers is essential for their correct operation, high computational efficiency, low-power solutions, and it is also key to get the most out of their capabilities with the hardware features that each of the microcontroller families has. There are different programming languages that can be used in microcontrollers, in this work we will focus on C and Assembler. C is one of the most widely used due to its efficiency and its ability to control the hardware directly. Assembly is a low-level language that allows more control over the instructions executed in the microcontroller, two songs have been implemented in assembler and C languages and the resources used for their execution on a Microchip PIC16F877 have been analyzed. The research results allow the developer to obtain results for a selection of the optimal hardware platform as well as the programming language according to the required memory utilization. Coding performed in MPLAB software with the asm and XC8 compilers, indicate that the C-code programs cover a larger amount of memory close to 4 times greater or higher.

Optimized LoRaWAN Architectures: Enhancing Energy Efficiency and Long-Range Connectivity in IoT Networks for Sustainable, Low-Power Solutions and Future Integrations with Edge Computing and 5G

The Internet of Things (IoT) has expanded rapidly, allowing for a network of sensors and gadgets to collect and share information to make people's lives easier and more convenient. As the Internet of Things (IoT) grows, however, energy efficiency becomes a major issue, especially for portable and wireless gadgets. Low-power, long-range communication capabilities are needed, and Long-Range Wide Area Network (LoRaWAN) has emerged as a viable solution to meet this need. This study provides an in-depth analysis of the LoRaWAN-based, low-power Internet of Things. The suggested network architecture is optimized for low power consumption and high connectivity for numerous Internet of Things (IoT) use cases. This low-power Internet of Things network relies on LoRaWAN gateways, end devices, and a server to function. LoRaWAN is a technology that enables the low-power, long-range transmission of data packets. The results show that the optimized case and non-optimized case have a delivery ratio of 0.85 to 0.73 from node 100 to 500. LoRaWAN significantly reduces energy usage compared to conventional IoT connectivity alternatives, making it a fantastic option for battery-powered devices in far-flung or limited-resource locations. Finally, the adoption of LoRaWAN provides a viable solution to address the energy efficiency concerns in IoT networks, hence allowing for sustainable, long-lasting IoT installations and enabling a wide variety of new applications within the IoT ecosystem. Furthermore, addresses the potential applications of this technology in the future, including upgrades and integration with other technologies like edge computing and 5G networks.

AviEar: An IoT-based Low Power Solution for Acoustic Monitoring of Avian Species

AviEar: An IoT-based Low Power Solution for Acoustic Monitoring of Avian Species