Low-power Receiver Architecture Research Articles

Low power receiver architectures for multi-carrier CDMA

The implementation of multi-carrier code division multiple access (MC-CDMA) receivers in digital hardware is considered. A low power algorithm is proposed which treats the received signal as a block of symbols, rather than processing the symbols individually. This reduces power by holding one input to the multiplier circuits used in the multi-carrier combiner multiplication constant for a number of clock cycles. This produces a 50% reduction in power consumption for a multi-user detection combiner circuit. This algorithm is also extended to the fast Fourier transform (FFT) block and allows an overall power drain reduction of 13% for the whole receiver. A software configurable version of the circuit, which allows a trade-off between power reduction and processing delay, is also described.

A Low Power Receiver Architecture for 4 Mbps Infrared Wireless Communication

A high performance and low power architecture is devised for a 4 Mbps infrared wireless communication system dedicated to mobile computing. In this architecture, 4PPM (4-Pulse Position Modulation) infrared signals detected by an infrared receiver are digitized into TTL interface level pulses, and the digitized pulses are demodulated by a 1-bit digital demodulator. To extend the range of the link length, a 4PPM demodulator is synthesized to implement a demodulation algorithm which is constructed so as to accommodate the output tolerance of the infrared receiver. A part of the experimental results shows that the proposed 4 Mbps infrared communication system can achieve an error free link in the range of 0–140 cm at power consumption of 245 mW and 65 mW for transmitting and receiving, respectively. The communication controller is integrated in a 0.6 μm CMOS standard-cell chip which contains 10,015 transistors on a 12 mm2 die.