Low-power Parallel Research Articles

Capacitor-Less Low-Power Neuron Circuit with Multi-Gate Feedback Field Effect Transistor

Recently, research on artificial neuron circuits imitating biological systems has been actively studied. The neuron circuit can implement an artificial neural network (ANN) capable of low-power parallel processing by configuring a biological neural network system in hardware. Conventional CMOS analog neuron circuits require many MOSFETs and membrane capacitors. Additionally, it has low energy efficiency in the first inverter stage connected to the capacitor. In this paper, we propose a low-power neuron circuit with a multi-gate feedback field effect transistor (FBFET) that can perform integration without a capacitor to solve the problem of an analog neuron circuit. The multi-gate FBFET has a low off-current due to its low operating voltage and excellent sub-threshold characteristics. We replace the n-channel MOSFET of the inverter with FBFET to suppress leakage current. FBFET devices and neuron circuits were analyzed using TACD and SPICE mixed-mode simulation. As a result, we found that the neuron circuit with multi-gate FBFET has a low subthreshold slope and can completely suppress energy consumption. We also verified the temporal and spatial integration of neuron circuits.

A two-level network-on-chip architecture with multicast support

It is essential for implementing processing systems of edge computing, internet of things (IoT) and wireless multimedia sensor networks (WMSN) to use low-power parallel and distributed architectures with high speed and low power consumption. Most of the artificial intelligence and machine learning applications need to be executed on efficient distributed architectures with multicast support. In this paper, TLAM, a high-performance and low-cost NoC architecture is proposed. TLAM stands for Two-Level network-on-chip Architecture with Multicast support and includes a hybrid path/tree based multicast routing algorithm and a specific two-level mesh topology. The routing algorithm of TLAM is basically working according to the Hamiltonian paths. In the proposed architecture, the topology is partitioned and the two-level links provide an efficient infrastructure for low-cost and low-latency transmission of multicast and broadcast messages between partitions. In TLAM, in addition to multicasting routing algorithm, hardware components for handling multicasting packets are designed in order to achieve performance improvements. The goal is to improve the efficiency and performance, especially latency, while handling both unicast and multicast packets. Experimental evaluations including network-level and router-level analysis with different configurations under various traffic patterns were performed. The evaluations in terms of latency, throughput, area and power consumption, indicate that TLAM provides higher performance, especially for dense multicasting and broadcasting, in comparison with the existing architectures.

Online Quartz Crystal Microbalance Analyzing Device of Mass Concentration of Formaldehyde Gas Based On FPGA

As one of the main indoor gas pollutants, formaldehyde gas (HCHO) seriously threatens human health and ranks second among toxic chemicals in China. In order to monitor the concentration of formaldehyde in the environment in real time, an online Quartz Crystal Microbalance (QCM) analyzing device based on FPGA is developed in this paper. This device is composed of QCM sensor module and FPGA signal processor. Firstly, graphene oxide film is prepared on QCM chip to adsorb formaldehyde, which causes the change of resonance frequency. Secondly, to monitor the quality of adsorbed formaldehyde through frequency change, FPGA signal processor is mainly integrated with Direct Digital Synthesis module, Analogue-to-Digital Conversion module, Low-Pass Filter module and Frequency Domain Analysis module. These modules have the characteristics of high speed, low power consumption and parallel processing, which provide the best solution for the online implementation of the analyzing device. Finally, the standard gas experiment shows that the device is feasible and reliable for the analysis of formaldehyde gas mass concentration, with a resolution of about 10 counts per 1% concentration.

Synaptic Device based on Resistive Switching Memory using Single-walled Carbon Nanotubes

Recently, research has been conducted on a biomimetic system called artificial neural networks (ANNs) to overcome the limits of Von Neumann’s system. Spiking neural networks (SNNs) in ANNs are hardware systems that implement NNs’ low-power parallel processing. The electrical characteristics of synaptic devices, which affect learning and memory, are important in SNN construction. Synaptic devices based on resistive switching are called memristors and have sufficient learning capabilities, such as spike-timing-dependent plasticity gradual switching [1]. However, memristors require high switching voltages and currents, resulting in high power consumption. To reduce the operation voltage of the synapse, new materials must be developed for the switching oxide and metal electrode. The conventional memristor structure comprises metal-oxide-metal (MOM) or metal-oxide-N+Si (MOS). This study proposes a synaptic device with single-walled carbon nanotubes (SWCNTs) with excellent electrical and mechanical properties to lower the switching voltage and fabricate a metal-oxide-SWCNTs-N+Si (MOCS)-structured synaptic device using SWCNTs as a metal electrode, as shown in Fig. 1 [2]. Finally, the electrical characteristics of MOM, MOS, and MOCS structures are analyzed and compared.

Detector Processor for a 5G Base Station.

Nonlinear soft bit detection is essential for the uplink receivers of 5G base stations, especially for users around the cell edge. However, its throughput and computing complexity are always challenges for both research and industry. A low-cost and low-power parallel implementation of a soft-output detector based on sorted QR decomposition (SQRD) and the K-best breadth-first search algorithm is thus proposed to reduce computational complexity and latency. In addition, to save area and reduce latency, two improvement methods are used: (1) reduce the computing cost by saturating and truncating large values during PED computing and (2) reduce the sorting cost by using the binary bit sorting method for a reduced sample set with finite accuracy. Furthermore, a pipelined VLSI architecture is designed using 28-nm digital CMOS technology offered by Semiconductor Manufacturing International Corporation (SMIC). It can achieve a peak throughput of 6400 Mbps while consuming 153 K gates (including all flip-flops) for SMIC’s 28-nm technology and running at 800 MHz, a 32% cost reduction compared with the published reference design.

Hardware-based spiking neural network architecture using simplified backpropagation algorithm and homeostasis functionality

Bio-inspired hardware-based spiking neural networks (SNNs) has been suggested as a promising computing system with low power consumption and parallel operation. We propose the supervised on-chip training method approximating the backpropagation algorithm and the pulse scheme applicable to the hardware-based SNNs with the low memory dependency. The performance evaluation through the MNIST data set classification shows that the proposed system achieves a similar recognition rate compared to that of the software-based network. In addition, we also propose novel homeostasis functionality using bias synapse to achieve high performances. The homeostasis functionality well regulates the firing rate of the neurons and improves the recognition rate. The TFT-type flash memory cells are used as synaptic devices. A fully connected two-layer neural network with non-leaky integrate-and-fire (I&F) neurons is used in the simulation. We then investigate the effect of the variation of the hardware-based network on the recognition rate. The simulation results show that the proposed system is resistant to weight variation because on-chip training is adopted.

An Enhanced Power Regulation and Seamless Operation Mode Transfer Control Through Cooperative Dual-Interfacing Converters

Both voltage control method (VCM) and current control method (CCM) have been well-developed to control DG units in a microgrid. Although conventional VCM has seamless operation mode transfer capability, it has slow power control dynamics in grid-tied operation. On the other hand, CCM features rapid power control but it can hardly provide voltage support during standalone operation of microgrids. To address these issues, a single DG unit is interfaced to the microgrid with two low power parallel converters. One converter is controlled by VCM while the other one is regulated by CCM. Through a new collaborative power control algorithm for these two converters in a single DG unit, the merits of both VCM and CCM are preserved. First, the power control dynamics of this DG unit can be significantly improved in grid-tied operation. Second, the load demand can be accurately shared by these two interfacing converters during islanding operation. Finally, a true seamless operation mode transfer is obtained at any time instant without preparations. Evaluation results from a three-phase prototype show that the proposed interfacing converter configuration and corresponding control algorithm are more suitable for microgrid applications.

A 0.3 pJ/bit 20 Gb/s/Wire Parallel Interface for Die-to-Die Communication

A high-density low-power parallel I/O for die-to-die communication is presented. The proposed interface includes a low-power transceiver and a high-density low-cost silicon interposer. The link architecture exploits single-sided and capacitive termination, passive equalization in the transmitter, and CMOS logic-style circuits to reduce the power consumption. To achieve a high bump/wire efficiency, single-ended signaling is used. A 4-layer Aluminum silicon interposer is fabricated providing 2.5 mm and 3.5 mm links between prototype transceivers. The transceiver prototype includes 3 transmitters and 3 receivers fabricated in 28 nm STM FD-SOI CMOS technology. The parallel interface operates at 20 Gb/s/wire and 18 Gb/s/wire data rates over the 2.5 mm and 3.5 mm channels with 5.9 and 7.7 dB of loss relative to DC (10.7 and 13.5 dB total loss) at $f_{bit}/2$ while consuming 0.30 and 0.32 pJ/bit excluding clocking circuits, respectively.

A Throughput-Optimized Optical Network for Data-Intensive Computing

Data-intensive computing increasingly involves operations at the scale of an entire computing system, requiring quick and efficient processing of massive datasets. In this article, the authors present a circuit-switched network architecture, together with requisite optical-switch and burst-mode transceiver technology, designed to support demanding graph algorithms in a distributed-memory system. The proposed optical network, configured as multiple planes of high-radix wavelength-division-multiplexed (WDM) switches, offers tremendous path diversity and is designed to deliver up to 10 terabytes per second of node bandwidth and predictable performance under heavy load with latencies well under a microsecond. With the optical core switch, the authors overcome pin-count and power-dissipation limitations of electrical networks with comparable bandwidth. To achieve this, they are developing new hardware, including nanosecond-scale silicon photonic switches with flip-chip-attached optical amplifiers, low-power parallel WDM transceivers operating at about 20-Gbps per channel, with burst-mode clock and data recovery circuits in advanced CMOS for link retraining in tens of nanoseconds. Network simulations predict that the proposed system could achieve graph performance on par with today's leading supercomputers, and its limited power consumption would result in several orders of magnitude of efficiency improvements that could allow the system to fit within a few racks.

Implementation of Improved Hash and Mapping Modified Low Power Parallel Bloom Filter Design

In this article, the authors present an investigation on bloom filters and introduce a new improved variant, which uses a secure modified hash function and suggested improved mapping scheme with an efficient parallel architecture. This novel architecture provides efficient, relatively fast membership querying and compact information representation with negligible false positive. This is relatively a low power and secure design with very less false positive ratio when compared with the traditional bloom filters. The design has been evaluated and tested using Xilinx 65 nm Virtex-5 field-programmable gate array as the target technology. The performance matrices are false positive ratio, power, speed and compactness.

A Comparative Performance Analysis of Low Power Bypassing Array Multipliers

Low power design of VLSI circuits has been identified as vital technology in battery powered portable electronic devices and signal processing applications such as Digital Signal Processors (DSP). Multiplier has an important role in the DSPs. Without degrading the performance of the processor, low power parallel multipliers are needed to be design. Bypassing is the widely used technique in the DSPs when the input operand of the multiplier is zero. A Row based Bypassing Multiplier with compressor at the final addition of the ripple carry adder (RCA) is designed to focus on low power and high speed. The proposed bypassing multiplier with compressor shows high performance and energy efficiency than Kuo multiplier with Carry Save Adder (CSA) at the final RCA.

A Low Power Parallel Sequential Decoder for Convolutional Codes

A novel decoding algorithm having a simple hardware realization is proposed for convolutional codes. The proposed decoder accepts a simple implementation in hardware in terms of area occupancy and power consumption compared to other decoders for convolutional codes such as those based on the Viterbi algorithm (VA). Furthermore, the processing delays due to looking back and forward in a trellis as in sequential decoding algorithms are avoided, which makes the proposed decoder suitable for fast high data rates wireless communication systems. Simulation results show a comparable bit error rate (BER) performance to optimal decoders with a reduction of power consumption of 60% compared to Viterbi decoders.

A Digitally Enhanced Dynamically Reconfigurable Analog Platform for Low-Power Signal Processing

We present a field-programmable analog array designed for accurate low-power mixed-signal computation. This 25-mm2 350 nm-CMOS reconfigurable analog IC incorporates digital enhancements to increase compatibility in embedded mixed-signal systems. The chip contains 78 computational analog blocks (CABs) which house a variety of processing elements. There are 36 general CABs with hundreds of common analog primitives for computation, 18 digital-to-analog converter (DAC) CABs, each with 8-b compilable DAC capabilities, and 24 vector-matrix multiplier CABs, for low-power parallel processing. A floating-gate routing matrix connects these analog elements to one another, both within individual CABs and between CABs. To facilitate digital interfacing and dynamic reconfigurability, we included a novel network of volatile switches based on digital shift and select registers that control analog switches. These dynamically controlled switches span all of the rows and columns of the internal routing, allowing for run-time system modification and scanning I/O. The digital registers can also double as on-chip memory. We introduce a new hybrid floating-gate switch matrix, which includes switches that eliminate previously observed mismatch issues to provide highly precise computation. To highlight the potential of this digitally enhanced analog processor, we demonstrate a dynamically reconfigurable image transformer, an arbitrary waveform generator, and a mixed-signal FIR filter.

NEW NOISE-BASED LOGIC REPRESENTATIONS TO AVOID SOME PROBLEMS WITH TIME COMPLEXITY

Instantaneous noise-based logic can avoid time-averaging, which implies significant potential for low-power parallel operations in beyond-Moore-law-chips. However, in its random-telegraph-wave representation, the complete uniform superposition (superposition of all N-bit binary numbers) will be zero with high probability, that is, non-zero with exponentially low probability, thus operations with the uniform superposition would require exponential time-complexity. To fix this deficiency, we modify the amplitudes of the signals of L and H states and achieve an exponential speedup compared to the old situation. Another improvement concerns the identification of a single product-string (hyperspace vector). We introduce "time shifted noise-based logic", which is constructed by shifting each reference signal with a small time delay. This modification implies an exponential speedup of single hyperspace vector identification compared to the former case and it requires the same, O(N) complexity as in quantum computing.

A low voltage and low power parallel electronically tunable resistor with linear and nonlinear characteristics

In this paper a bilateral resistive circuit is designed and presented with is work as a positive and negative electronically tunable resistor and has zero DC offset. The proposed topology is designed by paralleling two electronically tunable resistors to obtain lower resistive values and decreasing nonlinearity percent. The proposed topology is low voltage and low power and with proper transcurrent circuit, its current–voltage characteristics can be linear, expansive (square) and compressive (square root). Its supply voltages are ±1V and its dynamic range is ±1V too. The designed circuit is simulated in an industrial 65nm CMOS process. The linear version is tunable over the wide resistance range of 7kΩ–37GΩ.

A Study on Surge and Stall under the Interaction of Parallel Axial flow fan in Tunnel

In the ventilation design for tunnels above 10km, an axial flow fan of great power needs to be set in ventilation shafts. There are few provisions on the setting modes and less discussion of parallel axial flow fan mode in the Specifications for Design of Ventilation and Lighting of Highway Tunnels. All of these bring a lot of difficulties about the axial fan selection, layout and control design. There is no specialized research on axial flow fan for tunnels and no studies on surge and stall under the interaction of parallel axial flow fan in tunnel in spite of the more and more application of parallel axial flow fan. So, this paper conducts a study on surge and stall under the interaction of parallel axial flow fan in tunnels. Through the study on the operating principle and analysis of parallel axial flow fan, we can know that the noise will increase suddenly, which will in turn result in fan vibration and running instability once the stall occurs. When a fan surges, the air volume and pressure, the motor current will fluctuate sharply, which brings significantly increased vibration and noise. At the same time, the rotary blade and the shell are subject to considerable stress effects and the fan will possibly suffer from great damage. The surge will occur in the unstable zone of axial fan performance curve. The strong pulsation and periodic oscillation of the air flow will increase the noise, which is a serious damage to the fan. So an axial fan should avoid this zone in running. With two axial flow fans of the same power parallel, the mutual influence is not very great. Therefore this research will focus on the efficiency in the case of two fans with a high and a low power parallel. Stall will occur if the outside pressure is greater than the outlet pressure. Once the stall happens, the noise will increase suddenly, which will in turn result in fan vibration and running instability. When two fans parallel, i.e. when the power ratio of the parallel fans is over 5.3, the possibility of the small fan's stall is high, otherwise it is small. With regard to the running efficiency of parallel axial flow fans and the starting safety, it is better to parallel two fans, and the fans with adjustable movable vanes or frequency control or the ordinary nonadjustable fans can be used.

Design of Low Power Parallel Multiplier

Recent trends in the signal processing applications have created a need for energy efficient computation. Multiplication is a major power consuming circuit in many application areas like DSP, cryptography, and communication. This paper presents a novel architecture for the radix-2 recoded multiplier where we remove sign extended bits. The architecture is further optimized using proposed Booth Recoding Unit for low power applications. It is done by reducing switching activity on the inputs to the multiplication unit to reduce overall switching activity and hence the dynamic power consumption. We also propose an Adder-Subtractor circuit with reduced switching activity. Test Results show that the proposed design consumes 4 times less power and 15% less area than a conventional radix-2 low power recoded multiplier.

Low power multipliers based on new hybrid full adders

Five hybrid full adder designs are proposed for low power parallel multipliers. The new adders allow NAND gates to generate most of the multiplier partial product bits instead of AND gates, thereby lowering the power consumption and the total number of needed transistors. For an 8×8 implementation, the ALL-NAND array multiplier achieves 15.7% and 7.8% reduction in power consumption and transistor count at the cost of a 6.9% increase in time delay compared to standard array multiplier. The ALL-NAND tree multiplier exhibits lower power consumption and transistor count by 12.5% and 7.3%, respectively, with a 4.4% longer time delay, compared to conventional tree multiplier.

Low-power parallel multiplier with column bypassing

A low-power parallel multiplier design, in which some columns in the multiplier array can be turned-off whenever their outputs are known, is proposed. This design maintains the original array structure without introducing extra boundary cells, as was the case in previous designs. Experimental results show that it saves 10% of power for random input. Higher power reduction can be achieved if the operands contain more 0's than 1's.

Frequency spectrum based low-area low-power parallel FIR filter design

Parallel (or block) FIR digital filters can be used either for high-speed or low-power (with reduced supply voltage) applications. Traditional parallel filter implementations cause linear increase ...