Low-power Operational Transconductance Amplifier Research Articles

A High Gain, Low Power Operational Transconductance Amplifier Capable of Recording and Processing ECG Signals

Based on high output resistor current mirrors and differential pair inputs, a new operational transconductance amplifier (OTA) is designed in this paper that can collect, filter, denoise and amplify electrocardiogram (ECG) signals. The OTA is designed on a 0.18μm CMOS process with a supply voltage of 1.8V. In this experiment, the ECG signal generated by the human model is first simulated, which has a noise of 50 Hz from electromagnetic interference, especially the electrical power lines. The differential input pair is then connected to the model, and it is proved that it can denoise the common-mode noise. Finally, the designed OTA is connected to the manikin, and the experimental results are compared with the traditional OTA. The design achieves a differential-mode gain of 43.56dB and a common-mode gain of -31.36dB while maintaining a differential input voltage swing of 1Vpp. Experimental results show that the OTA can denoise and amplify the ECG signal without distortion.

Design Optimization of Ultra Low Power Operational Transconductance Amplifier With Nano TFETS Using Push–Pull Structure For Bias Current Optimization

Design Optimization of Ultra Low Power Operational Transconductance Amplifier With Nano TFETS Using Push–Pull Structure For Bias Current Optimization

A Biasing Approach to Design Ultra-Low-Power Standard-Cell-Based Analog Building Blocks for Nanometer SoCs

This paper presents an approach to design analog building blocks for nanometer systems on a chip (SoCs) that are based on digital standard-cells. The proposed approach guarantees that all the CMOS inverters, taken from a standard-cell library, operate with well-defined quiescent current and output voltage, thus allowing the implementation of analog circuits with good robustness against PVT variations. The approach is based on an Analog Body Bias Generator (ABBG) reusable block, similar to the ones adopted in digital applications to cope with process variations, and exploits the bulk terminals of both the p-channel and n-channel MOS transistors of the standard-cell inverter as current and voltage control inputs. The bulk voltages generated by the ABBG are routed to all the standard-cell inverters used for analog functions and allow to set the quiescent current of each cell to a multiple of a reference current and the static output voltage of each cell to half the supply voltage. The full custom design of the ABBG is presented, as well as the design flow to allow the automatic place and route of the proposed standard-cell based analog building blocks. We finally give an example of application trough the design of a fully synthesizable four-stage-gain low-power operational transconductance amplifier (OTA). Both the body bias generator and the OTA have been implemented in a 65-nm CMOS technology. The OTA nominal current consumption is <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.75~\mu \text{A}$ </tex-math></inline-formula> with 0.41- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{A}$ </tex-math></inline-formula> standard deviation. Good robustness against supply and temperature variations is also found.

Low Power-High Gain Bulk-Driven 3 Stages CMOS Miller OTA in 130nm Technology

The requirement of low-power analog circuits has been raised in recent years due to the strict limitation of power consumption in modern applications. Therefore, the trend in analog circuit design has been changed such that they are able to meet the required specifications with lower power dissipation. Design of low power operational transconductance amplifiers, which are the main building blocks in many analog applications, has been more pronounced to keep the power dissipation below certain levels. In this concern, this study presents a low power, high-performing bulk-driven 3 stages CMOS OTA in a 130 nm standard CMOS technology. The proposed circuit leverages the bulk-driven architecture at the input stage; thus it can operate under sub 1-V. The design process of the proposed OTA is explained in detail and the results are validated via post-layout simulations. The proposed OTA is powered by ±0.45 V symmetric voltage sources, where the power consumption is around 27 μW. The area overhead is only 0.0017μm2. The open-loop gain, unity gain frequency, and the phase margin are 73.24 dB, 5.167MHz, and 78o, respectively. To demonstrate the performance of the proposed circuit, a comparison is made with other circuits published in the last five years considering the well-known figures of merit (FOMs). Comparison results indicate that the proposed solution outperforms the other circuits for small-signal operation while it is the runner-up for large-signal operation.

Subthreshold biased enhanced bulk-driven double recycling current mirror OTA

This paper presents a single-stage bulk-driven double recycling low-voltage low-power operational transconductance amplifier (OTA) operating in subthreshold region. The proposed OTA utilizes double recycling topology and provides enough open loop voltage gain, slew rate, and unity gain frequency (UGF). The flipped voltage follower-based adaptively biased input differential pair working in class AB mode has ensured dynamic current boosting and increased slew rate. Further, the proposed OTA has utilized partial positive feedback to mitigate some of the performance reduction caused by the bulk-driven topology. The simulation results of the proposed OTA have ensured open loop gain of 79.5 dB, UGF of 37.1 kHz, and phase margin of 64°. It operates with dual power supply of ± 0.25 V and consumes low power of 60 nW. These performance parameters validate its usefulness for LV, LP and low-frequency applications. The process, voltage, and temperature variation effects on low-frequency voltage gain, UGF, and phase margin of the proposed OTA has also been investigated with process corner simulations. The proposed OTA is designed and simulated in UMC 180 nm standard n-tub bulk CMOS process technology utilizing Tanner EDA tools.

A design of an ultra low-power operational transconductance amplifier

This paper describes a design of an ultra low-power, low-voltage operational transconductance amplifier (OTA). A two stage OTA is implemented in 0.13 μ m SiGe BiCMOS technology. The OTA operates with all transistors active in subthreshold region. Under the typical operating conditions, circuit supply voltage is 0.5 V, supply current 150 nA and power consumption is 75 nW. Low-frequency gain is 53 dB, gain-bandwidth product (GBW) 350 kHz and phase margin 55°. -1 dB gain compression point is -7.4 dBm and output intercept point (OIP3) -21.5 dBm. OTA layout active chip area is 0.0014 mm2.

Realization of current-mode biquadratic filter employing multiple output OTAs and MO-CCII

This paper presents a low voltage low power operational transconductance amplifier circuit. By using a source degeneration technique, the proposed realization powered at ±0.9V shows a high DC gain of 63dB with a unity gain frequency at 3.5MHz, a wide dynamic range and a total harmonic distortion of −60dB at 1MHz for an input of 1Vpp. According to the connection of negative current terminal to positive voltage terminal of double output OTA circuit, a second generation current conveyor (CCII-) has been realized. This circuit offers a good linearity over the dynamic range, an excellent accuracy and wide current mode of 56MHz and voltage mode of 16.78MHz cut-off frequency f-3dB.Thereafter, new SIMO current-mode biquadratic filter composed by OTA and CCII as active elements and two grounded capacitors is implemented. This filter is characterized by (i) independent adjusting of pole frequency and quality factor, (ii) it can realize all simulations results without changing the circuit topology, (iii) it shows low power consumption about 0.24mW. All simulations are performed by Cadence (Cadence Design Systems) technology Tower Jazz 0.18μm TS18SL.

Low-power operational transconductance amplifier with slew-rate enhancement based on non-linear current mirror

This paper presents a high slew-rate operational transconductance amplifier (OTA) based on a non-linear current mirror which dramatically reduces the quiescent current. The proposed circuit achieves less quiescent current than previously proposed architectures since no additional bias branches are needed. The compactness of the proposed architecture does not require so much silicon area as other more complex adaptive bias architectures. The proposed technique is compared with previous state of the art high slew-rate architectures. Additionally, this novel architecture was used to design a non-symmetrical OTA which was part of the feedback loop of a switched-capacitor DC---DC converter. This OTA occupies 420 μm2 fabricated in a 130 nm technology. Measurements results are presented showing that a slew-rate enhancement, from 1.5 to 535 mV/μs, is achieved in an OTA biased with 50 nA and loaded with 50 pF.

A Novel Low Voltage Low Power OTA Based on Level Shifter Current Mirror

In this paper, a low voltage low power operational transconductance amplifier (OTA) structure is proposed. To achieve the low voltage low power operation, level shifter current mirrors are employed in the circuit structure. The proposed structure operates at ±0.5 V as supply voltages and dissipates power as 83 µW. Positive and negative slew rate of the circuit is 223 V/µs and 162 V/µs, respectively. Furthermore, the bandwidth of the circuit is about 80 MHz. The designed OTA is simulated with 0.18 µm TSMC CMOS technology parameters using SPICE. Simulation results have been justified the theoretical approach.DOI: http://dx.doi.org/10.5755/j01.eee.21.2.115011

Low-voltage, low-power operational transconductance amplifier using novel current-mirrors

ABSTRACTIn this paper, a new complementary metal oxide semiconductor (CMOS) low-voltage, low-power operational transconductance amplifier (OTA) using current-reuse-current- mirror (CRCM) based on chartered 0.18 μm CMOS technology is presented. Because of the new CRCM technique and negative resistance load used in the OTA, the post-layout simulation results demonstrate that the CRCM OTA achieves DC gain of 48.1 dB, gain-bandwidth product of 117 MHz, phase margin of 62°; while the power consumption is only 45.58 μW with ± 0.7 V supply voltages. Moreover, in the current-reuse stage, the passive resistors are replaced by n-channel MOS transistors, which not only make the OTA consists of only active MOS transistors, but also make the DC gain of the OTA can be electronically and continuously controlled by the bias voltage, and the tuning range is from 0 to 48.1 dB. The chip area including test pads is only 0.09×0.12 mm2. The cadence post-layout simulation results are provided to verify all the theoretical analysis.

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

LOW VOLTAGE, LOW POWER CHEBYSHEV FILTER IN 0.18 μm CMOS TECHNOLOGY

This paper presents an active-RC continuous time filter in 0.18 μm standard CMOS technology intended to operate on a very low supply voltage of 0.5 V. The filter designed, has a 5th order Chebyshev low pass response with a bandwidth of 477 kHz and 1-dB passband ripple. A low-power operational transconductance amplifier (OTA) is designed which makes the filter realizable. The OTA uses bulk-driven input transistors and feed-forward compensation in order to increase the Dynamic Range and Unity Gain Bandwidth, respectively. The paper also presents an equivalent circuit of the OTA and explains how the filter can be modeled using descriptor state-space equations which will be used for design centering the filter in the presence of parasitics. The designed filter offers a dynamic range of 51.3 dB while consuming a power of 237 μW.

A 0.9 V Supply OTA in 0.18 μm CMOS Technology and Its Application in Realizing a Tunable Low-Pass Gm-C Filter for Wireless Sensor Networks

A low voltage low power operational transconductance amplifier (OTA) based on a bulk driven cell and its application to implement a tunable Gm-C filter is presented. The linearity of the OTA is improved by attenuation and source degeneration techniques. The attenuation technique is implemented by bulk driven cell which is used for low supply voltage circuits. The OTA is designed to operate with a 0.9 V supply voltage and consumes 58.8 μW power. A 600 mVppd sine wave input signal at 1 MHz frequency shows total harmonic distortion (THD) better than -40 dB over the tuning range of the transconductance. The OTA has been used to realize a tunable Gm-C low-pass filter with gain tuning from 5 dB to 21 dB with 4 dB gain steps, which results in power consumptions of 411.6 to 646.8 μW. This low voltage filter can operate as channel select filter and variable gain amplifier (VGA) for wireless sensor network (WSN) applications. The proposed OTA and filter have been simulated in 0.18 μm CMOS technology. Corner case and temperature simulation results are also included to forecast process and temperature variation affects after fabrication.

An ultra low power OTA with improved unity gain bandwidth product

An operational transconductance amplifier (OTA) using dynamic threshold MOS (DTMOS) and hybrid compensation technique is presented in this paper. The proposed topology is based on a bulk and gate driven input differential pair. Two separate capacitors are employed for the OTA compensation where one of them is used in a signal path and the other one in a non-signal path. The circuit is designed in the 0.18μm CMOS TSMC technology. The proposed design technique shows remarkable enhancement in unity gain-bandwidth and also in DC gain compared to the bulk driven input differential pair OTAs. The Hspice simulation results show that the amplifier has a 92dB open-loop DC gain and a unity gain-bandwidth of 135kHz while operating at 0.4V supply voltage. The total power consumption is as low as 386nW which makes it suitable for low-power bio-medical and bio-implantable applications.

Ultra Low Power Improved Differential Amplifier

In this paper, a low voltage and ultra low power operational transconductance amplifier (OTA) is presented. As will be shown, the transient response and open loop gain of the proposed OTA are improved using adaptive biasing and DC gain enhancement techniques. The contributions of the proposed OTA are ultra low power consumption (only 3.977 μw), low supply voltages (±0.6 V), high swing, high speed, and high gain. It can clearly be seen that for the proposed OTA, the gain of the differential half-circuit in the input stage (A d ), DC gain (A 0), gain bandwidth (GBW), and slew rate (SR) are increased, whereas the settling time (T S ) is decreased. The results of simulations done using 0.18 μm Silterra CMOS process technology and the measurement results are presented to validate and compare the advantages of this work and other related works.

0.5 µW Sub-Threshold Operational Transconductance Amplifiers Using 0.15 µm Fully Depleted Silicon-on-Insulator (FDSOI) Process

We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design.

Design Optimization of High-Speed and Low-Power Operational Transconductance Amplifier Using gm/ID Lookup Table Methodology

We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125MS/s pipeline A/D converter implemented in a 0.18µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.

An Ultra Low-Voltage and Low-Power OTA Using Bulk-Input Technique and Its Application in Active-RC Filters

This paper presents the design of a two-stage bulk-input pseudo-differential operational transconductance amplifier (OTA) and its application in active-RC filters. The OTA was designed in 90 nm CMOS process and operates at a single supply voltage of 0.5 V. Using a two-path bulk-driven OTA by the combination of two different amplifiers the DC gain and speed of the OTA is increased. Rail-to-rail input is made possible using the transistor’s bulk terminal as in input. Also a Miller-Feed-forward (MFF) compensation is utilized which is improved the gain bandwidth (GBW) and phase margin of the OTA. In addition, a new merged cross-coupled self-cascode pair is used that can provide higher gain. Also, a novel cost-effective bulk-input common-mode feedback (CMFB) circuit has been designed. Simplicity and ability of using this new merged CMFB circuit is superior compared with state-of-the-art CMFBs. The OTA has a 70.2 dB DC gain, a 2.5 MHz GBW and a 70.8o phase margin for a 20 PF capacitive load whereas consumes only 25 µw. Finally, an 8th order Butterworth active Biquadrate RC filter has been designed and this OTA was checked by a typical switched-capacitor (SC) integrator with a 1 MHz clock-frequency.