Abstract
We present a low voltage, low power operational transconductance amplifier (OTA) designed using a Fully Depleted Silicon-on-Insulator (FDSOI) process. For very low voltage application down to 0.5 V, two-stage miller-compensated OTAs with both p-channel MOSFET (PMOS) and n-channel MOSFET (NMOS) differential input have been investigated in a FDSOI complementary metal oxide semiconductor (CMOS) 150 nm process, using 0.5 V threshold transistors. Both differential input OTAs have been designed to operate from the standard 1.5 V down to 0.5 V with appropriate trade-offs in gain and bandwidth. The NMOS input OTA has a simulated gain/3 dB-bandwidth/power metric of 9.6 dB/39.6 KHz/0.48 µW at 0.6 V and 46.6 dB/45.01 KHz/10.8 µW at 1.5 V. The PMOS input OTA has a simulated metric of 19.7 dB/18.3 KHz/0.42 µW at 0.4 V and 53 dB/1.4 KHz/1.6 µW at 1.5 V with a bias current of 125 nA. The fabricated OTAs have been tested and verified with unity-gain configuration down to a 0.5 V supply voltage. Comparison with bulk process, namely the IBM 180 nm node is provided and with relevant discussion on the use of FDSOI process for low voltage analog design.
Highlights
The growth in the area of portable biosensors, handheld wireless devices and implanted medical devices has created more interest in low power circuits [1]
What is unique in this paper is that the results show that similar performance can be achieved in a fully depleted process with potential for even lower power consumption due to better sub-threshold slope
Other work in the Fully Depleted Silicon-on-Insulator (FDSOI) process have demonstrated the performance of an RF amplifier not to be degraded for lower VDD supplies when the body is left floating [14], but here the matching of the differential pairs is of primary concern
Summary
The growth in the area of portable biosensors, handheld wireless devices and implanted medical devices has created more interest in low power circuits [1]. Silicon-On-Insulator (SOI) technology is being proposed as the node in the design of low power digital Very Large Scale Integration (VLSI) circuits This technology allows for further decrease in power and heat dissipation by, first, extending the trend in minimizing the voltage supply and, second, by reducing the capacitance; as the insulated localized “body” reduces the capacitance and minimizes the required charge to create the channel. These two benefits lower the dynamic power, which for digital circuits is approximately proportional to CV2f, where C is the sum total of all the capacitances in the circuit, V is the power supply, and f is the frequency of operation. We expect that these benefits will carry over to analog circuits if appropriate analog-favorable options such as high transconductance, higher output impedance, etc. can be provided in these processes; eventually allowing one to achieve a mixed-signal system on chip (SoC) solutions
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