Low-power Operational Amplifier Research Articles

Design Methodology for a Low-Power Two-Stage CMOS Operational Amplifier for Optical Receiver Applications

Design Methodology for a Low-Power Two-Stage CMOS Operational Amplifier for Optical Receiver Applications

The Design of Low Power Op-amp for Biomedical Application

This work presents a low-power operational amplifier (op-amp) circuit design which optimized and tailored specifically for biomedical circuit application in low power environment. The proposed op-amp design incorporates the folded cascode differential amplifier technique with a low voltage supply 1.2 V, utilizing current biasing, current mirrors, and adopted low-power circuit topologies. AC and DC analysis are carried out to analyse the performance of the proposed design. Extensive simulations executed using industrial standard EDA tool have validated the circuit design, and demonstrated a gain of 70.94 dB, UGBW of 4.90 MHz, GM of 52.70 dB, PM of 82.02 degrees, PSRR of 82.77 dB, CMRR of 100.78 dB, and total power dissipation of only 28.07 mW. Low power consumption is essential for biomedical circuit applications, and the result shows a significant power reduction without compromising other performance parameters. The proposed op-amp circuit design is suitable to be implemented in low-power and high-performance biomedical devices.

A 65 nm CMOS rail-to-rail auto-zero operational amplifier based on charge pump internal power supply

A high-gain, low-offset, and low-power auto-zero operational amplifier with rail-to-rail input/output is proposed. Based on a time-interleaved charge pump high-voltage on-chip internal power supply, the PMOS differential pair input configuration will achieve a rail-to-rail input range with constant transconductance. Time-interleaved auto-zero continuously eliminates the input offset voltage of the operational amplifier in the time domain. An nA-level bias circuit to realize low power. The operational amplifier circuit is based on a 65 nm CMOS process. Under 1.2V power supply voltage and temperature 27 °C, the input offset voltage of the operational amplifier is 3.16 μV and the input offset current is less than 20 pA. The temperature drift coefficient of offset voltage is 0.005 μV/°C between −40 °C and 90 °C. The variation rate of input transconductance is only 5.6 % among the rail-to-rail input range. The equivalent DC gain is 106.4 dB, the unit gain bandwidth is 0.54 MHz, the phase margin is 76.5°, and the power consumption is about 0.19 mW. The layout area is 0.83 × 0.75 mm2.

An Auto Adjustable Transimpedance Readout System for Wearable Healthcare Devices

The objective of this work was to design a versatile readout circuit for patch-type wearable devices consisting of a Transimpedance Amplifier (TIA). The TIA performs Current to Voltage (I–V) conversion, the most widely used technique for amperometry and impedance measurement for various types of electrochemical sensors. The proposed readout circuit employs a digitally controllable feedback resistor (Rf) technique in the TIA to improve accuracy, which can be utilized in a variety of electrochemical sensors within a current range of 0.1 µA–100 µA. It is designed to accommodate multiple sensors simultaneously to track multiple target analytes for high accuracy and versatile usage. The readout circuit consists of low power operational amplifier (op–amp) and digital circuit blocks, is designed and fabricated with Magna 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) technology, which provides low power consumption and a high degree of integration. The design has a small size of 0.282 mm2 and low power consumption of 0.38 mW with a 3.3 V power supply, which are desirable factors in wearable device applications.

Development of single channel EEG Acquisition system for BCI applications

Brain-Computer Interface (BCI) plays a major role in current technologies such as rehabilitation, control of devices, and various medical applications. BCI or brain-machine interface provides direct communication between a brain signal and an external device. In this paperwork, a detailed survey was carried out with the design of single-channel EEG system for various applications. Also, this paper mainly focused on the development of single-channel electroencephalography (EEG) signal acquisition system which includes a preamplifier, bandpass filter, post-amplifier and level shifter circuits. The design of the preamplifier and post-amplifier circuit was carried out by integrated circuits (IC) such as instrumentation amplifier IN128P and bandpass filter with the help of low power operational amplifier LM324. The developed single-channel acquisition board was tested by acquiring an electrooculogram (EOG) signal with closed and opened eye conditions. The acquired signal is displayed and stored in the computer with the help of the HBM-DAQ unit.

A Versatile Design of Low Power and High-Speed Operational Amplifier using Nano Scale Transistors

This paper illustrates the design of low power and high-speed operational Amplifier using Nanoscale Transistors. The proposed design introduces biasing block, for generating I=10uA for Channel length=180nm Technology. Adding biasing block to two-stages operational Amplifier current is constant i.e. there are no fluctuations in power supply, increase in bandwidth and power dissipation is less as compared the previous result. The design is simulated in p-spice tool and performed AC analysis. After analysis, the design achieved the parameter like Gain = 40db, Phase Margin=90º, Unity Gain Band Width=13MHz, Output Swing=0.1v to 1.7v and Power Dissipation=0.145mW.

An Ultra-Low-Power, 16 Bits CT Delta-Sigma Modulator Using 4-Bit Asynchronous SAR Quantizer for Medical Applications

In this paper, a low-power second-order feed-forward capacitor-structure continuous-time [Formula: see text] modulator with a 4-bit asynchronous successive approximation register (SAR) quantizer is presented. Through the utilization capacitor structure in the proposed modulator, first, the summation node of the integrators’ outputs and the feed-forward signals is implemented within the second integrator to reduce power consumption by eliminating an active summing amplifier. Second, the proposed architecture can compensate for the quantizer delay without using any excess inner digital to analog converter (DAC). In this design, the modulator applies two different low-power operational amplifiers. These advantages cause the modulator to consume very low power and achieve a favorable figure of merit (FOM) value. In fact, in this paper, the combination of the previously reported methods and designs and doing required reforms has led to a new design with better performance, especially in power reduction. The designed modulator which is simulated using 0.18[Formula: see text][Formula: see text]m CMOS technology achieves 95.98[Formula: see text]dB peak signal-to-noise and distortion (SNDR) for 10[Formula: see text]KHz signal bandwidth and dissipates 44[Formula: see text][Formula: see text]w while its FOM is obtained about 43 fJ/conv.-step.

A $64.8~\mu$ W > 2.2 G $\Omega$ DC–AC Configurable CMOS Front-End IC for Wearable ECG Monitoring

This paper presents a low-power and high input impedance dc–ac configurable CMOS front-end integrated circuit (IC) for wearable ECG monitoring. This IC mainly includes three parts, namely: 1) high input impedance dc-coupled instrumentation amplifier; 2) AC-coupled programmable gain amplifier; and 3) low-power single operational amplifier continuous-time $\Sigma \Delta $ modulator. In addition, on-chip power management and clock generator were implemented to minimize the device size of the ECG monitoring system. This IC can be configured to dc-coupled topology to achieve ultra-high input impedance for dry electrode, and ac-coupled topology to achieve better electrode dc offset suppression for wet electrode. A baseline wander tracking technique is proposed to eliminate baseline disturbance, and a right-leg-driven circuit is realized to enhance the common-mode rejection ratio and minimize the 50/60 Hz power line interference. Fabricated in 0.18- $\mu \text{m}$ CMOS process, this front-end IC occupies 0.24 mm2 active area and consumes 64.8 $\mu \text{W}$ from a 1.8-V supply. It achieves peak SNR 54.7 dB, spurious free dynamic range 58.2 dB, input impedance higher than 2.2 $\text{G}\Omega $ , and dc suppression as large as ±300 mV.

Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications

Design of a low-power CMOS operational amplifier with common-mode feedback for pipeline analog-to-digital converter applications

Low Power High Gain Amplifier for Low Voltage Wearable Biomedical Applications

In this paper, A High Gain Low Power Operational Amplifier was designed in main for the usage of in biomedical applications. The amplifier is designed to produce high gain with less power consumption. The PMOS input transistors are used with high gate areas which operate in subthreshold or cutoff region helps in reduction of flicker noise. Later switched bias is used to further reduce noise levels by making input transistors switch between cutoff and inversion regions. This switched bias helps in reduction of noise with less power, thus helps in low power usage in reduction of noise. The supply voltage is ±1.5V with average gain of the amplifier is 87dB in required frequency range and CMRR of about 128dB. The unity gain frequency is 5.3MHz and cutoff frequency is 43.6KHz. Average power consumption of the model is 24.8μW. The model is designed using TSMC-180nm process, in the S-Edit of Tanner EDA. The simulations are carried under different temperatures i.e. 25o,36.9o (body temperature) and 40o. This amplifier is intended to amplify neural spikes which are in low amplitudes(mV) and in frequency range of about 5-100Hz.

Ultra low-voltage ultra low-power memristor based band-pass filter design and its application to EEG signal processing

Memristor has been claimed as the passive fourth fundamental circuit element in 1971. About four decades later, a physical realization which presents memristor behavior has resulted in significant interest on memristor and it is continuing to increase at a growing rate. Memristor can provide new possibilities in analog circuit design thanks to its properties which cannot be mimicked by older passive circuit elements. Since no practically available memristor exist on the market yet, obtaining of a practical implementation which behaves like a memristor is important from the point of view real-world circuit design. In this paper, an ultra low-voltage ultra low-power DTMOS-based memristor design is presented. Ultra low-voltage, ultra low-power operational amplifier and ultra low-voltage, ultra low-power multiplier are also designed to use in the implementation. Memristor design is composed of these two type active blocks using CMOS 0.18 µm process technology with symmetric ?0.25 V supply voltages. Our memristor is used in a second order Sallen---Key band-pass filter topology. Designed memristor-based Sallen---Key band-pass filter is then used for real electroencephalogram data processing. The simulation results show that the design of adjustable memristor memristance/memductance provides tunable filter parameters and without any significant distortion with appropriate parameter set even at ultra-low power levels and at very-low frequencies.

Low Area, Low Power and Wide Bandwidth Operational Amplifier by 130nm CMOS Technology

Low Area, Low Power and Wide Bandwidth Operational Amplifier by 130nm CMOS Technology

Note: Wide band amplifier for quartz tuning fork sensors with digitally controlled stray capacitance compensation.

We presented a preamplifier design for quartz tuning fork (QTF) sensors in which the stray capacitance is digitally compensated. In this design, the manually controlled variable capacitor is replaced by a pair of varicap diodes, whose capacitance could be accurately tuned by a bias voltage. A tuning circuit including a single side low power operational amplifier, a digital-to-analog converter, and a microprocessor is also described, and the tuning process can be conveniently carried out on a personal computer. For the design, the noise level was investigated experimentally.

A 32 ppm/°C temperature-compensated operational amplifier for application in medical device tracking

This paper presents a low-power, low-noise and high precision operational amplifier for a tracking system containing the intelligent medical device, and is an extended version of paper previously published by Nenadovic et al. in proc. of ICECS 2014. The accuracy of the tracking system strongly depends on the accurate amplitude acquisition of the received signal. Therefore, an operational amplifier with precise gain control and effective temperature compensation has been designed and fabricated. The operational amplifier provides linear and temperature independent signal amplification at frequencies between 0.2 and 20 kHz at a body temperature. The amplifier shows measured gain over temperature sensitivity as low as 32 ppm/°C in temperature range from 20 to 40 °C and consumes 300 μA from a supply voltage of 2.5 V. Furthermore, the measured gain over temperature sensitivity in the range from ?40 to 130 °C is only 60 ppm/°C. Simulated linearity for signal amplitudes up to 10 mV is 0.4 % and the input-referred noise at 1 kHz is 32 nV/?Hz. An open-loop gain of 46 dB at 1 kHz and bandwidth-gain product of 4.8 MHz is measured. The operational amplifier was designed in IHPs 250 nm SiGe BiCMOS technology and occupies an area of 0.2 mm2.

Low Power Operational Amplifier in 0.13um Technology

Low power is one of the most indispensable criteria in several of application. In this paper a low power operational amplifier consists of two stages and operates at 1.8V power. It is designed to meet a set of provided specification such as high gain and low power consumption. Designers are able to work at low input bias current and also at low voltage due to the unique behavior of the MOS transistors in sub-threshold region. This two-stage op-amp is designed using the Silterra 130nm technology library. The layout has been draw and its area had been calculated. The proposed two stage op-amp consists of NMOS current mirror as bias circuit, differential amplifier as the first stage and common source amplifier as the second stage. The first stage of an op-amp contributed high gain while the second stage contributes a moderate gain. The results show that the circuit is able to work at 1.8V power supply voltage (VDD) and provides gain of 69.73dB and 28.406MHz of gain bandwidth product for a load of 2pF capacitor. Therefore, the power dissipation and the consistency of this operational amplifier are better than previously reported operational amplifier.

Design of 0. 13um CMOS Low Voltage Rail to Rail Fully Differential Operational Amplifier Review

An operational amplifier is one of the most commonly used components in analog and digital circuit designs. Low voltage and low power operational amplifier design has become an increasingly interesting subject as many applications switch to portable battery powered operations. The need for design techniques to allow amplifiers to maintain an acceptable level of performance when the supply voltages are decreased is immense. One of the most important features in low voltage amplifier designs is ensuring that the amplifier maintains constant behavior in the presence of rail-to-rail input common mode variations while providing a rail-to-rail output to maximize signal-to-noise ratio. As the supply voltage to a standard CMOS op-amp is reduced, the input common mode range and the output swing get reduced drastically. Special circuits have to be used to raise them up to rail-to-rail supply voltage. In this work we propose a design of a low-voltage CMOS rail-to-rail folded cascode operational amplifier to be realized in a standard 130 nm CMOS technology with 1.2V supply voltage and consumes power less than 400uW. A two stage miller compensated folded cascode op-amp has a UGB >10MHz and achieves a gain >80dB over almost full range of the common mode input voltage.

A Low Power Op Amp for 3-Bit Digital to Analog Converter in 0.18 m CMOS Process

Digital to (DAC) is used to get analog voltage corresponding to input digital data in VLSI circuit design with greater integration levels. However, providing linear current and voltage outputs with the use of strictly CMOS devices presents the need for a low power operational amplifier (op-amp) circuit. In this research, the analysis of op-amp circuit for 3-bit DAC is illustrated. In order to reduce the power dissipation, weighted resistor is utilized in the proposed design. To design the op-amp circuit for 3-bit DAC, the design has been implemented in CEDEC 0.18 μm CMOS process. The simulated result shows that, under 8 V as the supply voltage the total power dissipation for the proposed DAC is 43.6 nW. Moreover, 143.17 μm is found as the total chip area of the designed op-amp circuit for 3-bit DAC.

A Novel Low Voltage, Low Power and High Gain Operational Amplifier Using Negative Resistance and Self Cascode Transistors

In this work a low power, low voltage and high gain operational amplifier is proposed. For this purpose a negative resistance structure is used in parallel with output to improve the achievable gain. Because of using self cascode transistors in the output, the proposed structure remains approximately constant in a relatively large output voltage swing causing an invariable gain. To evaluate the proposed method an op amp was designed in 0.18μm CMOS technology. The simulation results showed a gain of 84dB, unity gain bandwidth of 12.45MHz and phase margin of 81 degree; with 1V power supply and 1pF load capacitor.

4H-SiC Lateral JFET for Low Power Operational Amplifier Applications

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Design of CMOS Instrumentation Amplifier

A low power CMOS instrumentation amplifier used for biomedical applications is presented in this paper. It consists of a low power operational amplifier with CMFC structure. By analysis and optimization of the parasitic effects and parameters, instrumentation amplifier has better performance in every aspect. This simulation result shows that, in the case of guaranteed bandwidth, the amplifier can suppress flicker noise interference effectively. The instrumentation amplifier designed in 0.5μm CMOS technology with 3.3V power supply shows a dynamic range of 70.1dB and 23.48ns settling time within 0.05% accuracy. The main amplifier dissipates 10.5mW power. It also includes a bias circuit that dissipates 2.2mW power.