Low-power Nonvolatile Memory Applications Research Articles

Wake-up free ferroelectric hafnia-zirconia capacitors fabricated via vacuum-maintaining atomic layer deposition

Ferroelectric hafnium-zirconium oxide (HZO) is an excellent candidate for low-power non-volatile memory applications due to its demonstrated ferroelectricity at the nanoscale and compatibility with silicon-based technologies. The interface of HZO in contact with its electrode, typically TiN in a metal–ferroelectric–metal (MFM) capacitor configuration, is of particular interest because factors, such as volume confinement, impurity concentration, interfacial layers, thermal expansion mismatch, and defect trapping, are believed to play a crucial role in the ferroelectric performance of HZO-based devices. Processing variables, such as precursor type, oxygen source, dose duration, and deposition temperature, are known to strongly affect the quality of the oxide–metal interface. However, not many studies have focused on the effect of breaking or maintaining vacuum during MFM deposition. In this study, sequential, no-atmosphere processing (SNAP) is employed to avoid atmospheric exposure, where electrode TiN and ferroelectric HZO are deposited sequentially in the atomic layer deposition chamber without breaking vacuum. The effect of breaking vacuum during the sequential deposition steps is elucidated by fabricating and characterizing MFM capacitors with and without intentional vacuum breaks prior to the deposition of the HZO and top TiN. Using x-ray photoelectron spectroscopy and time-of-flight secondary ion mass spectrometry (ToF-SIMS), we reveal that breaking vacuum after bottom TiN electrode deposition leads to interfacial oxidation and increased carbon contamination, which preferentially stabilizes the non-ferroelectric tetragonal phase and lead to diminished remanent polarization. Avoiding carbon impurities and interfacial TiOx at the HZO and TiN interface using SNAP leads to heightened remanent polarization, reduced leakage current density, and elimination of the wake-up effect. Our work highlights the effect of vacuum breaking on the processing-structure-properties of HZO-based capacitors, revealing that maintaining vacuum can significantly improve ferroelectric properties.

Reliability aspects of ferroelectric TiN/Hf0.5Zr0.5O2/Ge capacitors grown by plasma assisted atomic oxygen deposition

The reliability of Hf0.5Zr0.5O2 (HZO) metal–ferroelectric–semiconductor capacitors grown by plasma-assisted atomic oxygen deposition on Ge substrates is investigated with an emphasis on the influence of crystallization annealing. The capacitors show very weak wake-up and imprint effects, allowing reliable operation in excess of 10 years, which is attributed partly to the clean, oxide-free Ge/HZO bottom interface. The weak temperature dependence and the observed asymmetries between polarization up and down states and between positive and negative coercive voltage shifts lead to the conclusion that imprint is controlled by carrier injection at the top electrode interface. The latter mechanism is associated with trapping at interfacial oxygen-vacancy defects. On the other hand, using ultrafast (millisecond) flash annealing improves the leakage current by at least an order of magnitude and the endurance by a factor of 3 compared to conventional rapid thermal annealing, which makes them suitable for low power nonvolatile memory applications where (ultra)thin HZO is an essential requirement.

Scaling down of cobalt quantum‐dots by colloidal route for non‐volatile memory device application

The present work details the synthesis of cobalt quantum-dots (Co QDs) with size downscaling to 1–2 nm and their applications in non-volatile memory (NVM) devices. The process of colloidal synthesis is simple and provides the control over a wide range of QDs size. The scaled-down colloidal Co QDs are applied for the NVM device fabrication. Colloidal synthesised Co QDs are spin-coated over silicon dioxide wafer for the fabrication of floating-gate NVM devices. Capacitance–voltage (C–V) and capacitance–time (C–t) measurements of the fabricated NVM device indicate a low voltage operation of device. A sweep voltages as small as 1.2–4 V lead to a flat band voltage shift of 0.35–1.5 V, evidencing the low operating voltage and low power NVM applications. Further, retention characteristics show a robust retention by fabricated NVM device. In addition, C–V measurements are done for the several samples in order to study the process repeatability. The work also is compared with the other processes for the floating gate memory device.

Interface Modification of Bernal- and Rhombohedral-Stacked Trilayer-Graphene/Metal Electrode on Resistive Switching of Silver Electrochemical Metallization Cells

Bernal- and rhombohedral-stacked trilayer graphene (B- and r-TLG) on nickel (Ni) and iridium (Ir) films acting as bottom electrodes (BEs) of silver electrochemical metallization cells (Ag-EMCs) have been investigated in this study. Prior to the fabrication of the EMC devices, Raman mapping and atomic force microscopy are applied to identify the B- and r-TLG sheets, with the latter revealing a significant D peak and a rough surface for the Ir film. The Ag-EMCs with the stacked BE of r-TLG on the Ir film show a conductive mechanism of Schottky emission at the positive top electrode bias for both high- and low-resistance states that can be examined by the resistance change with the device area and are modulated by pulse bias operation. Thus, an effective electron barrier height of 0.262 eV at the r-TLG and Ir interface is obtained because of the conspicuous energy gap of r-TLG on the Ir film and the van der Waals (vdW) gap between the r-TLG and Ir contact metal. With the use of Ni instead of Ir contact metal, the Ag-EMCs with TLG BE demonstrate +0.3 V/-0.75 V operation voltages, more than 104 s data retention at 115 °C and 250 times endurance testing, making the TLG sheets suitable for low-power nonvolatile memory applications on flexible substrates.

Modeling and Design Space Exploration for Bit-Cells Based on Voltage-Assisted Switching of Magnetic Tunnel Junctions

The effect of voltage on the anisotropy of a magnetic tunnel junction (MTJ) is of substantial interest for low-power nonvolatile memory applications. In this paper, we develop a device-to-bit-cell level simulation framework for voltage-assisted switching of the MTJs, which can satisfactorily reproduce the published experimental data. Our simulation framework is based on a coupled Landau–Lifshitz–Gilbert–Slonczewski equation and nonequilibrium greens function formalism. Using this simulation framework, we investigate the effect of scaling the oxide thickness of an MTJ to enhance the electric field effect. Although it seems attractive for an isolated device, yet, in a bit-cell configuration, reducing the oxide thickness leads to an increase in the supply voltage. In addition, we demonstrate that the unipolar characteristic of the voltage-assisted switching leads to write failures depending on the initial state stored in the MTJ. We, therefore, suggest a read before write scheme exhibiting approximately $2\times $ improvement in the write energy consumption at a bit-cell level compared with a standard STT-MRAM for iso-oxide thickness. However, the latency overhead associated with voltage-assisted MTJs results in a $1.55\times $ degradation of the write speed. Moreover, our layout analysis indicates that the bit-cell area reduction is constrained by the metal pitch, in spite of smaller access transistors.

Self Current Limiting MgO ReRAM Devices for Low-Power Non-Volatile Memory Applications

We report an interface engineering approach to achieve a self-compliance controlled and forming-free switching in ReRAM devices based on MgO switching layers. The proposed devices showed scalability in self-compliance current with low set and reset voltages as the interfacial layer thickness was increased. The devices showed write endurance up to 1000 cycles under self-compliance controlled switching and demonstrated potential for ultra-fast switching with low switching energies. The mechanism behind self-compliant switching is explained and supported with capacitance-voltage measurement. We believe that these devices will not require compliance current limiting transistors which will allow massive densification of these devices.

Subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory for nonvolatile operation

A subthreshold-swing-adjustable tunneling-field-effect-transistor-based random-access memory (SAT RAM) has been proposed and fabricated for low-power nonvolatile memory applications. The proposed SAT RAM cell demonstrates adjustable subthreshold swing (SS) depending on stored information: small SS in the erase state (“1” state) and large SS in the program state (“0” state). Thus, SAT RAM cells can achieve low read voltage (Vread) with a large memory window in addition to the effective suppression of ambipolar behavior. These unique features of the SAT RAM are originated from the locally stored charge, which modulates the tunneling barrier width (Wtun) of the source-to-channel tunneling junction.

Homo-junction ferroelectric field-effect-transistor memory device using solution-processed lithium-doped zinc oxide thin films

High performance homo-junction field-effect transistor memory devices were prepared using solution processed transparent lithium-doped zinc oxide thin films for both the ferroelectric and semiconducting active layers. A highest field-effect mobility of 8.7 cm2/Vs was obtained along with an Ion/Ioff ratio of 106. The ferroelectric thin film transistors showed a low sub-threshold swing value of 0.19 V/dec and a significantly reduced device operating voltage (±4 V) compared to the reported hetero-junction ferroelectric transistors, which is very promising for low-power non-volatile memory applications.

Unipolar Resistive Switching Properties of Diamondlike Carbon-Based RRAM Devices

Resistance random access memory devices based on nanoscale diamondlike carbon (DLC) films are demonstrated. The devices exhibit excellent memory performances such as high on/off-resistance ratio (>; 300), high switching speed ( <; 50 ns), low operation voltage ( <; 1.2 V), low switching power consumption ( <; 16 μW), nondestructive readout, and good reliability. Nanoscale graphitic filament formation and rupture alternately through the field-induced dielectric breakdown and thermal fuse effect, respectively, are proposed to be responsible for the resistance switching. The unipolar switching characteristics shown here suggest that DLC is one of the most promising material candidates for high-density and low-power nonvolatile memory applications.

Microstructure and optical properties of phase-change Ge–Sb–Te nanoparticles grown by pulsed-laser ablation

Phase-change Ge–Sb–Te (GST) nanoparticles have been in-situ synthesized by a pulsed-laser ablation method. During the ablation process, growth parameters including temperature of heat treatment, pressure, and laser fluence are extensively explored. Scanning and transmission electron microscopy are used to study microstructure and phase formation of the nanoparticles. Fourier transform analysis of electron micrographs exhibits an evidence of existence of the stoichiometric single GST-225 phase. We have measured micro-Raman scattering spectra of commercially available GST-124, -147, and -225 bulk and GST nanoparticles. Lack of the amorphous Te–Te stretching mode near 150cm−1 from the Raman spectra of the bulk samples indicates that the samples are well-crystallized. From the measurements of GST nanoparticles with different growth conditions, we could get information towards the optimal growth conditions for better crystalline quality of the GST nanoparticles. Our results suggest that micro-Raman scattering spectroscopy can be used to study phases and phase changes in the GST bulk crystals and nanoparticles through local structural information, which is being developed for low-power non-volatile memory applications.