Low-power Market Research Articles

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor

An experimental 2.0-volt low-power PowerPC 601™ Microprocessor built in a modified 3.6-volt, 0.6-µm IBM CMOS technology is described. By using unmodified tasks from the 3.6-volt design, a 3× power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power market while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are deuced or eliminated. Challenges to this technique include I/O interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, a long with the experimental changes. The paper reviews the motivation behind low-power microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction.

NSC800 — a low-power high-performance microprocessor family

A new microprocessor family announced a year ago brings high performance to the traditionally low-performance low-power market. The NSC800 is a family of CMOS microprocessors fabricated in a new high-density, high-speed CMOS process designated P2 CMOS. Since these componets combine NMOS speed with CMOS power levels, the designer now need not make a trade-off decision: it is no longer necessary to turn down design opportunities simply because a processor with the performance capbilities required and low power consumption is not available

A performance/cost approach to transistor design

The customer is interested in the overall performance and the cost of transistors and this requires a more sophisticated design approach aimed at high performance at low cost. For the high-frequency high-power market, the transistor designer is technically limited in his choice of junction formation methods, and the cost of products is high. For those markets where many techniques compete, the performance/cost design approach is essential; the low-frequency low-power market particularly warrants this approach at this time. For the low-frequency low-power market, where several techniques can yield the same performance, the designer must consider the various methods of forming junctions and making contacts, and the mechanical design, including the housing, in terms of the cost factors. The various design elements will be described and analysed with respect to the cost factors reflected by process complexity, product reproducibility and design flexibility. Particular emphasis is placed on a comparison of the three basic junction-formation techniques?alloy, grown and diffused. This analysis indicates, on a performance/cost basis, that alloy and grown types of transistors have, and will have for many years, an important share of the computer, audio and broadcast radio-frequency and intermediate-frequency markets. Consideration of the high-frequency high-power markets, and the inevitable simplification of the relatively new diffusion process, leads to the conclusion that all three basic techniques will be required to obtain the broadest market coverage in the expanding transistor market.