Low Power High Speed Research Articles

A low-power high speed full adder cell using carbon nanotube field effect transistors

The adder circuit is basic component of arithmetic logic design and that is the most important block of processor architecture. Moreover, power consumption is the main concern for real-time digital systems. In recent times, carbon nanotube field effect transistors (CNTFET) used for arithmetic circuit designs with high performance. A creative substitute for highspeed, less power, and small size in area designs is the CNTFET. This paper presents 1- bit full adder with CNTFETs for low power and high performance. Using the computer aided design (CAD) tool the proposed 1-bit full adder design model is simulated using 32 nm with CNTFET technology, a voltage supply of +0.9V. Performance comparisons between various proposed designs and existing 1-bit full adder design have been made in terms of the delay, power, and power delay product (PDP). The proposed CNFET logic also design for n-bit carry look adder (CLA) and compare it to other CLAs to evaluate performance and reliability. The simulation results shows that the proposed adder consume less power than existing adders.

Design and Implementation of High Speed Low Power Decimation Filter for Hearing AID Applications

This work is focused on designing and implementing a decimation filter specifically intended for use in hearing aid applications. The filter utilizes distributed arithmetic (DA) and is described in this brief. Our proposal involves the development of a reconfigurable finite impulse response (FIR) filter, which utilizes both offset binary code (OBC) and binary distributed arithmetic (DA) techniques. Additionally, we utilize canonic signed digit (CSD) representation to develop decimation filters, which include the CIC filter, half band filter, and corrector filter. In this work, we have implemented a decimation filter using Matlab Simulink. We have utilized Xilinx Vivado 19.2 to execute the FIR filters, binary DA filters, and OBC DA-based filters. Our focus is on implementing these filters using VLSI architecture, in order to achieve low power consumption, reduced latency, less area, and fast speed.

A High Speed Low Power 10T SRAM with high Robustness

A High Speed Low Power 10T SRAM with high Robustness

Nanowire-based synaptic devices for neuromorphic computing

The traditional von Neumann structure computers cannot meet the demands of high-speed big data processing; therefore, neuromorphic computing has received a lot of interest in recent years. Brain-inspired neuromorphic computing has the advantages of low power consumption, high speed and high accuracy. In human brains, the data transmission and processing are realized through synapses. Artificial synaptic devices can be adopted to mimic the biological synaptic functionalities. Nanowire (NW) is an important building block for nanoelectronics and optoelectronics, and many efforts have been made to promote the application of NW-based synaptic devices for neuromorphic computing. Here, we will introduce the current progress of NW-based synaptic memristors and synaptic transistors. The applications of NW-based synaptic devices for neuromorphic computing will be discussed. The challenges faced by NW-based synaptic devices will be proposed. We hope this perspective will be beneficial for the application of NW-based synaptic devices in neuromorphic systems.

Comparison of Low Power High Speed Comparator for Flash ADC

The analog to digital converter (ADC), a bridge between digital world and analog world, plays a crucial role in the modern semiconductor industry. Among different types of ADCs, the flash ADC (also known as the direct-conversion ADC) is exceedingly fast, whose high sample rate enables many large bandwidth applications, such as optical communication, radar detection. The comparator circuit is one of the critical components of flash ADC. The characteristics, like latency, gain and power consumption, of comparators determine the overall performance of flash ADCs. This paper analyzes and compares different types of comparator architecture and suggests a high-performance design for flash ADC.

Optimization for Device Figure of Merit of Ferroelectric Tunnel FET using Genetic Algorithm

Tunnel FET is a gate-controlled, field effect transistor, followed band to band tunneling (BTBT) transport of charge carriers, having low subthreshold swing (SS < 60 Mv decade−1|T = 300 K). With tunnel FET, low-ION is a built-in problem, that limits its universal adaptability high-speed low-power uses. To overcome, this limitation of tunnel FET, a conventional double gate TFET has acquired for analysis having ferroelectric (BaTiO3)/HfO2 gate materials and source/channel region with Si1−xGex/Si semiconductor channel composition.The present device design techniques enhanced the ION and put down the subthreshold swing(SS). The analysis results by using the Silvaco simulator shows improvement in switching current(ION) approximately ∼103 times better than conventional DGTFET,without affecting the IOFF. Ultimately the change in ION∼order of 10−8 A μm−1 to 10−5 A μ has been measured for VDS ∼ 0.5 V at room temperature. The IOFF ( ∼10−20 A μm−1) has been measured. In addition to this, first time genetic algorithm has been used for the optimization of ferroelectric tunnel FET (Fe-Tunnel FET) device design parameters like a subthreshold swing (SS), ambipolar current (Iamb) and IONby using device deign parameters, doping (NS, ND), dielectric (εOX) and work function (WF).The research conclusion shows that Fe-Tunnel can play in lead backgroundfor super low power applications in advanced VLSI circuit and system.

An intelligent model for supporting edge migration for virtual function chains in next generation internet of things

The developments on next generation IoT sensing devices, with the advances on their low power computational capabilities and high speed networking has led to the introduction of the edge computing paradigm. Within an edge cloud environment, services may generate and consume data locally, without involving cloud computing infrastructures. Aiming to tackle the low computational resources of the IoT nodes, Virtual-Function-Chain has been proposed as an intelligent distribution model for exploiting the maximum of the computational power at the edge, thus enabling the support of demanding services. An intelligent migration model with the capacity to support Virtual-Function-Chains is introduced in this work. According to this model, migration at the edge can support individual features of a Virtual-Function-Chain. First, auto-healing can be implemented with cold migrations, if a Virtual Function fails unexpectedly. Second, a Quality of Service monitoring model can trigger live migrations, aiming to avoid edge devices overload. The evaluation studies of the proposed model revealed that it has the capacity to increase the robustness of an edge-based service on low-powered IoT devices. Finally, comparison with similar frameworks, like Kubernetes, showed that the migration model can effectively react on edge network fluctuations.

Classification of Acoustic Influences Registered with Phase-Sensitive OTDR Using Pattern Recognition Methods

This article is devoted to the development of a classification method based on an artificial neural network architecture to solve the problem of recognizing the sources of acoustic influences recorded by a phase-sensitive OTDR. At the initial stage of signal processing, we propose the use of a band-pass filter to collect data sets with an increased signal-to-noise ratio. When solving the classification problem, we study three widely used convolutional neural network architectures: AlexNet, ResNet50, and DenseNet169. As a result of computational experiments, it is shown that the AlexNet and DenseNet169 architectures can obtain accuracies above 90%. In addition, we propose a novel CNN architecture based on AlexNet, which obtains the best results; in particular, its accuracy is above 98%. The advantages of the proposed model include low power consumption (400 mW) and high speed (0.032 s per net evaluation). In further studies, in order to increase the accuracy, reliability, and data invariance, the use of new algorithms for the filtering and extraction of acoustic signals recorded by a phase-sensitive reflectometer will be considered.

The design of a low-power 4-bit barrel shifter for a current steering DAC using optimized multiplexers in 65 nm technology

CMOS technology scaling has paved the way for a faster and more complex integration. Low-power techniques have become crucial because of the demand for low power consumption and high speed. The main objective of this research is to utilize low-power techniques to implement a 4-bit barrel shifter that can shift or rotate data using any number of bits within a single cycle. Gate Diffusion Input (GDI), modified GDI, and full-swing GDI logic have been employed to implement a 2:1 multiplexer, among which the modified GDI-based multiplexer stands out because of its minimal power consumption. Consequently, a 4-bit barrel shifter is implemented using a modified GDI-based multiplier. All designs and simulations were performed using the Cadence Virtuoso tool in UMC 65 nm technology. This technology enables the accurate analysis and assessment of the designed barrel shifter, considering the characteristics and limitations of the 65 nm process. This study focused on leveraging low-power techniques to implement a 4-bit barrel shifter to address the industry's demand for power-efficient solutions. The modified GDI-based multiplexer is a promising choice that provides a balance between low power consumption and high performance. The use of advanced design tools and selected technology further ensures accurate simulations and evaluations of the proposed design.

Fine-Tuning the Performance of Ultraflexible Organic Complementary Circuits on a Single Substrate via a Nanoscale Interfacial Photochemical Reaction.

Flexible electronics has paved the way toward the development of next-generation wearable and implantable healthcare devices, including multimodal sensors. Integrating flexible circuits with transducers on a single substrate is desirable for processing vital signals. However, the trade-off between low power consumption and high operating speed is a major bottleneck. Organic thin-film transistors (OTFTs) are suitable for developing flexible circuits owing to their intrinsic flexibility and compatibility with the printing process. We used a photoreactive insulating polymer poly((±)endo,exo-bicyclo[2.2.1]hept-ene-2,3-dicarboxylic acid, diphenylester) (PNDPE) to modulate the power consumption and operating speed of ultraflexible organic circuits fabricated on a single substrate. The turn-on voltage (V on) of the p- and n-type OTFTs was controlled through a nanoscale interfacial photochemical reaction. The time-of-flight secondary ion mass spectrometry revealed the preferential occurrence of the PNDPE photochemical reaction in the vicinity of the semiconductor-dielectric interface. The power consumption and operating speed of the ultraflexible complementary inverters were tuned by a factor of 6 and 4, respectively. The minimum static power consumption was 30 ± 9 pW at transient and 4 ± 1 pW at standby. Furthermore, within the tuning range of the operating speed and at a supply voltage above 2.5 V, the minimum stage delay time was of the order of hundreds of microseconds. We demonstrated electromyogram measurements to emphasize the advantage of the nanoscale interfacial photochemical reaction. Our study suggests that a nanoscale interfacial photochemical reaction can be employed to develop imperceptible and wearable multimodal sensors with organic signal processing circuits that exhibit low power consumption.

A low power high speed single phase clock level restoring 16T master-slave flip-flop

PurposeA low power flip-flop circuit is designed for energy-efficient devices. Digital sequential circuits are in huge demand because every processor has most of the parts of digital circuit. The sequential circuits consist of a basic data storing element, a latch is used to store single bit data. The flip-flop takes a sufficient portion of the total chip area and overall power consumption as well. This study aims to the low power energy-efficient applications like laptops, mobile phones and palmtops.Design/methodology/approachThis paper proposes a new type of flip-flop that consists of the only 16 transistors with a single-phase clock. The flip-flop has two blocks, master and slave latch. In this design, the authors have focused on only master latch, which includes a level restoring circuit. It is used to help the master latch in data retention process. The latch circuit has two inverters in back-to-back arrangement. The proposed flip-flop is implemented on 65 nm complementary metal oxide semiconductor technology using Cadence Virtuoso environment and compared with other reported flip-flops.FindingsThe proposed flip-flop architecture outperformed the peak percentage, i.e. 79.25% as compared to transmission gate flip-flop and a minimum of 20.02% compared to 18 T true single phase clocking (TSPC) improvement in terms of power. It also improved C to Q delay and power delay product. In addition, by reducing the number of transistors the total area of the proposed flip-flop is reduced by a minimum of 13.76% with respect to 18TSPC and existing flip-flop. For reliability checking the Monte Carlo simulation is performed for thousand samples and it is compared with the recently reported 18TSPC flip-flop.Originality/valueThis work is tested by using a test circuit with a load capacitor of 0.2 fF. The proposed work uses a new topology to work as master-slave. Power consumption of this technique is very less and it is best suitable for low power applications. This circuit is working properly up to 2 GHz frequency.

Design and Analysis of CMOS Dynamic Comparator for High-Speed Low-Power Applications Using Charge Sharing Technique

Analog–digital converters (ADCs) are electronic circuits that convert continuous time signals into digital signals (binary data) for analyzing, estimation, and transmission. Transceivers use ADC in the baseband stage of receiver to convert the analog signals to digital form for further signal processing. At high-frequency applications, like millimeter wave applications, the ADC consumes more power due to the high sampling rate with respect to the increased bandwidth. In this article, a novel dynamic comparator is presented with delay and power analysis for the design. The expression is derived for all operational regions of the transistor. The new design is proposed for low-power consumption and reduced delay of the circuit. The novel design overcomes the drawbacks of the less operating frequency range, high latency, and more power dissipation of existing comparator designs. The proposed low-power dynamic comparator is simulated with 45 nm CMOS technology that provides total power dissipation of 33.92 µW, delay of 19.71 ps, and energy per conversion of 0.19 fJ/conv. with a supply voltage of 1 V.

A Future Perspective on In-Sensor Computing

Artificial intelligence (AI) is escalating rapidly in most applications nowadays. However, the current artificial hardware system couldn’t meet the demand of AI considering the energy and latency budget. The imaging hardware system is a crucial example, wherein more than 90% of the data generated by sensors is redundant and processed indiscriminately for AI applications like classification and recognition. Thus, lots of energy and time are wasted irrationally. Therefore, it is necessary to develop novel insensor computing architectures mimicking the functions of the human retina, which is highly intelligent and energy-efficient to deal with tremendous data. Most current practical vision chips (in image sensor computing chips) are based on CMOScompatible fabrication technologies. However, the sensing signals are in analog format, and the related memory and processing devices are bulky in size, making it challenging to build a large-scale neuro-network. Emerging technologies include developing 1, A new material system that is compact in size to deal with sensing and processing; 2, An advanced device structure that combines the sensing and computing functionalities. The ultimate goal for in-sensor computing is to achieve efficient artificial intelligent hardware that are low power consumption, high speed, high resolution, highaccuracy recognition, large-scale integration, and programmable.

Latch and flip-flop design in QCA technology with minimum number of cells

Today, the implementation of computer systems and digital circuits is done using CMOS (Complementary Metal-Oxide Semiconductor) technology, but problems such as high-power consumption and physical limitations of CMOS have led researchers to use the emerging technology of point cellular quantum automation (QCA). The most important features of this technology are very high density, low power consumption and high switching speed. In this paper, new structures for type D latch and flip-flops in quantum-dot cellular automat technology are presented.Initially, a majority gate-based D-latch was proposed with 19 cells, a cross-sectional area of 0.01 μm2, and a delay of 0.75 clock cycles. Then, using the proposed D-latch, the reset-based D-latch is also proposed, which has better properties than the previous structures and has only 19 cells, a cross-sectional area of 0.01 μm2 and a delay of 0.75 clock cycles. Also, using the proposed latch, a D-latch with a set and reset terminals is introduced, which has 21 cells, a delay of 0.75 clock cycles and an area of 0.01 μm2. In order to show that the ability of circuits in more complex designs, k properly, the proposed latches have been used to make, 3-bit shift register. The proposed methods are simulated using QCADesigner and QCAPro tools and compared with other designs in terms of cell number, area, latency, and power consumption.

Progress in ultrafast spintronics research

Ultrafast spintronics is one of the most promising fields for information processing technology innovation. When compared with traditional electronic devices, new spin-based devices have advantages such as low power consumption, high speed, and nonvolatility. Exploring novel physical phenomena and mechanisms relating to electronic spins significantly promotes the development of next-generation spintronic devices. In this review, we outline a sequence of advances in the fields of ultrafast magnetics and spintronics. First, a quick overview of spintronics and the discovery of ultrafast demagnetization induced by a femtosecond laser is provided. The proposed physical mechanisms and theories of ultrafast spin dynamics are then summarized, including the phenomenological three-temperature model, computations based on the time-dependent density functional theory, the Elliott-Yafet spin-flip mechanism, and the nonlocal superdiffusive spin transport model. Following that, the most recent experimental and theoretical studies on all-optical switching of ferrimagnetic and ferromagnetic metals are thoroughly reviewed. Furthermore, the discovery of hot-electron spin transport induced by ultrashort lasers as well as its influence on ultrafast magnetization dynamics, ultrafast spin transfer torque, spin injection into semiconductors, and spin accumulation and dissipation in hot-electron transport are described. The advancements in the optimization and manipulation of spintronics-based terahertz emitters are reviewed and analyzed. Finally, we discuss the current challenges in ultrafast spintronics research as well as possible future studies.

Multicore Photonic Complex-Valued Neural Network with Transformation Layer

Photonic neural network chips have been widely studied because of their low power consumption, high speed and large bandwidth. Using amplitude and phase to encode, photonic chips can accelerate complex-valued neural network computations. In this article, a photonic complex-valued neural network (PCNN) chip is designed. The scale of the single-core PCNN chip is limited because of optical losses, and the multicore architecture of the chip is used to improve computing capability. Further, for improving the performance of the PCNN, we propose the transformation layer, which can be implemented by the designed photonic chip to transform real-valued encoding to complex-valued encoding, which has richer information. Compared with real-valued input, the transformation layer can effectively improve the classification accuracy from 93.14% to 97.51% of a 64-dimensional input on the MNIST test set. Finally, we analyze the multicore computation of the PCNN. Compared with the single-core architecture, the multicore architecture can improve the classification accuracy by implementing larger neural networks and has better phase noise robustness. The proposed architecture and algorithms are beneficial to promote the accelerated computing of photonic chips for complex-valued neural networks and are promising for use in many applications, such as image recognition and signal processing.

Design of Low Power High Speed Hybrid Full Adder: A Review

In this research, I present a new hybrid FA design (a blend of CMOS and transistor logic types) that tries to achieve high speed while consuming minimal power, hence the low PDP designation. Our proposed FA and seven other current FA designs were modelled on the spice with a 45 nm low power model file, a standard test bed, and a standard test pattern (56 input switching), and the impersonation results for eight designs are equivalent. Power outages, distribution delays, and PDP are all issues that need to be addressed. The results of simulations show that our suggested FA design has the shortest broadcast delays and the lowest PDP across the whole power supply and frequency range.

Designing a Content-Addressable Memory Cell Using Multiplexer in Quantum-Dot Cellular Automata

Low power consumption, high density, regularity, and high speed are readily applicable to QCA. Therefore, memory is well suited for implementation using this technology. Because Content Addressable Memory (CAM) is a special type of memory structure used in very fast search applications, QCA can be used to design this memory at the nanoscale. In this paper, we introduce a new structure for the CAM cell. For this purpose, all the components needed to implement this memory cell are designed separately. In order to provide a structure with fewer gates, the operational equations of the components are considered in a way that they can be implemented by a unique multiplexer gate. For this purpose, a new multiplexer is used, which operates based on the Columbic interaction of cells. QCADesigner is used to simulate the proposed structures and verify their operation. The proposed structure has a 28% improvement in the number of cells and a 27% improvement in the occupied area.

A Low Power High Speed Accuracy Controllable Approximate Multiplier Design

Abstract: For energy effective and high performance design, the low power VLSI circuit is used. Multiplier is an essential part of low power VLSI design, since the effectiveness of the digital signal processor depends upon the multiplier. In multiplier circuit, utmost of the power is dissipated across in full adder circuits. Multiplication is one of the important process in microprocessor and there will be a lot of delay because of array multiplier, which can be compressed with the help of the column compressor approach. It uses a selection of half adders, full adders and compressors to sum the partial products in stages until two numbers are left. An 8 * 8 and 16 * 16 bit multiplier design is executed by assigning the adder and compressor. Partial product totality is the speed limiting operation in multiplication due to the propagation detention in adder networks. In order to reduce the propagation detention, compressors are introduced. Compressors calculate the sum and carry at each position concurrently. The attendant carry is added with a advanced significant sum bit in the coming stage. This is continued until the final product is generated. The partial product tree of the multiplier is estimated by the proposed tree compressor ( High Speed Compressor, Dual Stage Compressor, Exact Compressor). Keywords: Partial Products, Half Adder, Full Adder, High Speed Compressor, Dual Stage Compressor, Exact Compressor.

Booth Multiplier Based on Low Power High Speed Full Adder With Fin_FET Technology

This paper proposes a novel Fin FET-based HSFA for the multiplier in order to overcome the issues of low speed operation. It is advantageous to use Fin FETs to construct the arithmetic circuit while assessing the available works. The carry propagation and slow operation of the old technique are disadvantages. The CMOS-based compressor circuit, on the other hand, suffers from leakage current, which reduces its driving capabilities. High current DSP applications are well matched to the design's specifications. Even with a supply voltage of 1 volt, the proposed device has a decent driving capability. As a result, the circuit runs more quickly and has less latency. A transmission gate is used in the design of the suggested adder structure to selectively block or transfer data from the input to output. Half adder and adder are shown in the following illustrations. The smaller the transistor count, the less power it uses. The suggested Fin FET design for the smaller transistors has a superior driving capability than the CMOS equivalent. Additionally, when cascading, the Fin FET based adder may contribute to superior switch performance, such as when using ripple carry adder. There is also the possibility of a low operation, which may operate at Low wattage Electronic designs for high-performance and small devices have become increasingly dependent on the use of VLSI circuits. The power of a processor is determined in large part by the multiplier used in its design. Multiplier factor booth coding is being used to reorder the input bits in order to reduce facility use. The booth decoder works by rearranging the specified booth equivalent. The Booth decoder has the ability to expand the range of zeros. As a result, the power consumption of the design will be decreased even more. As soon as the input bit constant drops below zero, related rows or columns of an adder must be disabled, if possible.