Low-power Hardware Architecture Research Articles

Power-Saving 8K Real-Time AV1 Arithmetic Encoder Architecture

This article presents high-throughput and low-power hardware architecture versions for the arithmetic encoding block used in AV1 video codec.

Efficient Architectures for Full Hardware Scrypt-Based Block Hashing System

The password-based key derivation function Scrypt has been employed for many services and applications due to its protection ability. It has also been employed as a proof-of-work algorithm in blockchain implementations. Although this cryptographic hash function provides very high security, the processing speed and power consumption to generate a hashed block for the blockchain network are low-performance. In this paper, a high-speed and low-power hardware architecture of the Scrypt function is proposed to generate blocks for the Scrypt-based blockchain network. This architecture minimizes the number of main computational blocks to reduce the power consumption of the system. In addition, the proposed sharing resources and pipelined architectures make the calculation speed increase significantly while the hardware cost is reduced by half compared to the parallel non-pipelined architecture. The full hardware system is designed and implemented on Xilinx Virtex-7 and Aveo U280 FPGA platforms. The hash rate of the proposed system reaches 229.1 kHash/s. Its hash rate, hardware and energy efficiencies are much higher than those of the other works implemented on FPGA and GPU hardware platforms. The proposed hardware architecture is also successfully implemented in an ASIC design using ROHM 180 nm CMOS technology.

UltraTrail: A Configurable Ultralow-Power TC-ResNet AI Accelerator for Efficient Keyword Spotting

Recent advances in machine learning show the superior behavior of temporal convolutional networks (TCNs) and especially their combination with residual networks (TC-ResNet) for intelligent sensor signal processing in comparison to classical CNNs and LSTMs. In this article, we propose UltraTrail, a configurable, ultralow-power TC-ResNet AI accelerator for sensor signal processing and its application to efficient keyword spotting (KWS). Following a strict hardware/model co-design approach, we have derived an optimized low-power hardware architecture for generalized TC-ResNet topologies consisting of a configurable array of processing elements and a distributed memory with dynamic content reallocation. We additionally extend the network with conditional computing to reduce the number of operations during inference and to provide the possibility for power-gating. The final accelerator implementation in Globalfoundries' 22FDX technology achieves a power consumption of 8.2 μW for the task of always-on KWS meeting the real-time requirement of 100 ms per inference with an accuracy of 93% on the Google Speech Command Dataset.

Low‐complexity architecture for AR(1) inference

In this Letter, the authors propose a low-complexity estimator for the correlation coefficient based on the signed process. The introduced approximation is suitable for implementation in low-power hardware architectures. Monte Carlo simulations reveal that the proposed estimator performs comparably to the competing methods in the literature with maximum error in order of . However, the hardware implementation of the introduced method presents considerable advantages in several relevant metrics, offering more than 95% reduction in dynamic power and doubling the maximum operating frequency when compared to the reference method.

Lifting Based Object Detection Networks of Remote Sensing Imagery for FPGA Accelerator

The on-board object detection of remote sensing images is of great significance and challenges in both military and civilian fields. To achieved on-board object detection, we require a high-performance and low power hardware architecture. Inspired by the hardware implementation advantages of the lifting scheme in JPEG2000, we introduce the lifting scheme into object detection networks to promote the hardware implementation capability. Based on the equivalence between the lifting scheme and the convolution, we proposed a lifting based FPGA accelerator. The lifting scheme provides a parallel strategy for every convolutional layer to obtain high performance, and high resource utilization. The proposed accelerator can improve the throughput of networks, and promote the utilization efficiency of hardware resources. The experimental results on lifting based YOLOv3-tiny (LS-YOLOv3-tiny) show that the proposed accelerator has better power efficiency than other hardware implementation, and have better DSP efficiency than other FPGA-based designs.

Double SHA-256 Hardware Architecture With Compact Message Expander for Bitcoin Mining

In the Bitcoin network, computing double SHA-256 values consumes most of the network energy. Therefore, reducing the power consumption and increasing the processing rate for the double SHA-256 algorithm is currently an important research trend. In this paper, we propose a high-data-rate low-power hardware architecture named the compact message expander (CME) double SHA-256. The CME double SHA-256 architecture combines resource sharing and fully unrolled datapath technologies to achieve both a high data rate and low power consumption. Notably, the CME algorithm utilizes the double SHA-256 input data characteristics to further reduce the hardware cost and power consumption. A review of the literature shows that the CME algorithm eliminates at least 9.68% of the 32-bit XOR gates, 16.49% of the 32-bit adders, and 16.79% of the registers required to calculate double SHA-256. We synthesized and laid out the CME double SHA-256 using CMOS $0.18~\mu m$ technology. The hardware cost of the synthesized circuit is approximately 13.88% less than that of the conventional approach. The chip layout size is $5.9 mm \times 5.9 mm$ , and the correctness of the circuit was verified on a real hardware platform (ZCU 102). The throughput of the proposed architecture is 61.44 Gbps on an ASIC with Rohm 180nm CMOS standard cell library and 340 Gbps on a FinFET FPGA 16nm Zynq UltraScale+ MPSoC ZCU102.

Efficient Object Detection Framework and Hardware Architecture for Remote Sensing Images

Object detection in remote sensing images on a satellite or aircraft has important economic and military significance and is full of challenges. This task requires not only accurate and efficient algorithms, but also highperformance and low power hardware architecture. However, existing deep learning based object detection algorithms require further optimization in small objects detection, reduced computational complexity and parameter size. Meanwhile, the generalpurpose processor cannot achieve better power efficiency, and the previous design of deep learning processor has still potential for mining parallelism. To address these issues, we propose an efficient contextbased feature fusion single shot multibox detector (CBFFSSD) framework, using lightweight MobileNet as the backbone network to reduce parameters and computational complexity, adding feature fusion units and detecting feature maps to enhance the recognition of small objects and improve detection accuracy. Based on the analysis and optimization of the calculation of each layer in the algorithm, we propose efficient hardware architecture of deep learning processor with multiple neural processing units (NPUs) composed of 2D processing elements (PEs), which can simultaneously calculate multiple output feature maps. The parallel architecture, hierarchical onchip storage organization, and the local register are used to achieve parallel processing, sharing and reuse of data, and make the calculation of processor more efficient. Extensive experiments and comprehensive evaluations on the public NWPU VHR10 dataset and comparisons with some stateoftheart approaches demonstrate the effectiveness and superiority of the proposed framework. Moreover, for evaluating the performance of proposed hardware architecture, we implement it on Xilinx XC7Z100 field programmable gate array (FPGA) and test on the proposed CBFFSSD and VGG16 models. Experimental results show that our processor are more power efficient than general purpose central processing units (CPUs) and graphics processing units (GPUs), and have better performance density than other stateoftheart FPGAbased designs.

SensorNet: A Scalable and Low-Power Deep Convolutional Neural Network for Multimodal Data Classification

This paper presents SensorNet which is a scalable and low-power embedded deep convolutional neural network (DCNN), designed to classify multimodal time series signals. Time series signals generated by different sensor modalities with different sampling rates are first converted to images (2-D signals), and then DCNN is utilized to automatically learn shared features in the images and perform the classification. SensorNet: 1) is scalable as it can process different types of time series data with variety of input channels and sampling rates; 2) does not need to employ separate signal processing techniques for processing the data generated by each sensor modality; 3) does not require expert knowledge for extracting features for each sensor data; 4) makes it easy and fast to adapt to new sensor modalities with a different sampling rate; 5) achieves very high detection accuracy for different case studies; and 6) has a very efficient architecture which makes it suitable to be deployed at Internet of Things and wearable devices. A custom low-power hardware architecture is also designed for the efficient deployment of SensorNet at embedded real-time systems. SensorNet performance is evaluated using three different case studies including physical activity monitoring, stand-alone tongue drive system, and stress detection, and it achieves an average detection accuracy of 98%, 96.2%, and 94% for each case study, respectively. We implement SensorNet using our custom hardware architecture on Xilinx FPGA (Artix-7) which on average consumes 246- $\mu \text{J}$ energy. To further reduce the power consumption, SensorNet is implemented using application-specified integrated circuit at the post layout level in 65-nm CMOS technology which consumes approximately $8\times $ lower power compared to the FPGA implementation. In addition, SensorNet is implemented on NVIDIA Jetson TX2 SoC (CPU + GPU) and compared to TX2 single-core CPU and GPU implementations, FPGA-based SensorNet obtains $15\times $ and $4\times $ improvement in energy consumption.

Algorithm and VLSI Architecture Design of Low-Power SPIHT Decoder for mHealth Applications.

A real-time cost and power-efficient (CPE) set partitioning in hierarchical trees (SPIHT) decoder design with low hardware complexity and low-power dissipation is introduced in one-dimension (1-D) wavelet-based quality-assured electrocardiograph (ECG) compression systems for mobile health (mHealth) applications. However, current SPIHT coding architectures are designed for image/video processing. These architectures require a large amount of memory as well as complicated sorting algorithms, which both require time-consuming tasks and are unsuitable for mobile ECG applications. Based on our previously modified SPIHT coding work, which used flags and check bits to reduce memory requirements and coding complexity by merging three search processes into one step. Therefore, to achieve the real-time design goal for mobile ECG applications, in this paper, we first introduce a hardware-oriented SPIHT decoding algorithm that is suitable for decoding the previously presented SPIHT coding work. Accordingly, an appropriate low-power hardware architecture is developed to implement a real-time high-performance and low-cost SPIHT VLSI design for our proposed decoder algorithm, which is appropriate for mobile ECG applications. Using the distinct ECG signals in the MIT-BIH arrhythmia database (sampling rate of 360Hz), the final simulation and VLSI implementation results reveal that the proposed CPE SPIHT decoder design outperforms the state-of-the-art designs in terms of the average decoding time, the decoding quality, the VLSI speed, and the power consumption. Most importantly, the design can be exploited to a 1-D 1024 × 1 wavelet-based quality-assured ECG data compression system.

A Scalable Low-Power Reconfigurable Accelerator for Action-Dependent Heuristic Dynamic Programming

Adaptive dynamic programming (ADP) is an effective algorithm that has been successfully deployed in various control tasks. For many emerging applications where power consumption is a major design consideration, the conventional way of implementing ADP as software executing on a general-purpose processor is not sufficient. This paper proposes a scalable and low-power hardware architecture for implementing one of the most popular forms of ADP called action-dependent heuristic dynamic programming. Different from most machine-learning accelerators that mainly focus on the inference operation, the proposed architecture is also designed for energy-efficient learning, considering the highly iterative and interactive nature of the ADP algorithm. In addition, a virtual update technique is proposed to speed up the computation and to improve the energy efficiency of the accelerators. Two design examples are presented to demonstrate the proposed algorithm and architecture. Compared with the software approach running on a general-purpose processor, the accelerator operating at 175 MHz achieves 270 times improvement in computational time while consuming merely 25 mW power. Furthermore, it is demonstrated that the proposed virtual update algorithm can effectively boost the energy efficiency of the accelerator. Improvements up to 1.64 times are observed in the benchmark tasks employed.

Hardware-Friendly Actor-Critic Reinforcement Learning Through Modulation of Spike-Timing-Dependent Plasticity

In this work, we propose a hardware-friendly reinforcement learning algorithm. The learning algorithm is based on an actor-critic structure implemented with spiking neural networks (SNNs). A biologically plausible and hardware-friendly spike-timing-dependent plasticity learning rule is formulated and employed in the training of SNNs. Several important aspects of applying the learning rule in a reinforcement learning context is studied, especially from the circuit designers’ point of view. Pitfalls of potential noise mixing and correlated spikes are identified and properly addressed. To feature a low-power learning architecture, techniques such as down-sampling data for certain learning blocks, injecting quantization noise as noisy residues in neurons, and proper memory partitioning are proposed. A 1-D state-value function learning problem and a 2-D maze walking problem are examined in this paper to illustrate effectiveness of the proposed algorithm and learning rules. A low-power hardware architecture is proposed and examples are implemented with Verilog. Hardware complexity of the proposed algorithm is analyzed, and potential solutions to breaking memory bottleneck when the size of the problem gets large is also discussed.

Energy Efficiency for Ultrascale Systems: Challenges and Trends from Nesus Project

consumption is one of the main limiting factors for designing and deploying ultrascale systems. Therefore, this paper presents challenges and trends associated with energy efficiency for ultrascale systems based on current activities of the working group on Energy Efficiency in the European COST Action Nesus IC1305. The analysis contains major areas that are related to studies of energy efficiency in ultrascale systems: heterogeneous and low power hardware architectures, power monitoring at large scale, modeling and simulation of ultrascale systems, energy-aware scheduling and resource management, and energy-efficient application design.

Design and Implementation of Low-Power Hardware Architecture With Single-Cycle Divider for On-Line Clustering Algorithm

A dual-stage hardware architecture that supports two kinds of moving averages for the on-line clustering algorithm is proposed. The architectural design of this work is different from the one of previous works that focus on the iterative clustering algorithm. The system includes a set of memories that operates in ping-pong mode, so that the Manhattan distances can be computed when the centroids are updated. The high-throughput parallel divider in the moving-average engine is a new solution to reduce the computational time of one division operation to a single clock cycle and to calculate cumulative moving averages with no precision loss. Two hardware examples show the robustness of the proposed architecture, and the architectural analysis is performed with the 90 nm CMOS technology. In the first example, the gate count is the smallest and the normalized power consumption of this work is the lowest among previous works. In the second example, the architecture is compared with related works, which implement the Self-Organizing Map (SOM) algorithm. The proposed work has high flexibility for parameter combinations and can achieve high performance for color quantization in a single iteration. The functionalities of the proposed system are also verified with the background subtraction application.

Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

In this paper, we present and compare efficient low-power hardware architectures for accelerating the Packet Data Convergence Protocol (PDCP) in LTE and LTE-Advanced mobile terminals. Specifically, our work proposes the design of two cores: a crypto engine for the Evolved Packet System Encryption Algorithm (128-EEA2) that is based on the AES cipher and a coprocessor for the Least Significant Bit (LSB) encoding mechanism of the Robust Header Compression (ROHC) algorithm. With respect to the former, first we propose a reference architecture, which reflects a basic implementation of the algorithm, then we identify area and power bottle-necks in the design and finally we introduce and compare several architectures targeting the most power-consuming operations. With respect to the LSB coprocessor, we propose a novel implementation based on a one-hot encoding, thereby reducing hardware’s logic switching rate. Architectural hardware analysis is performed using Faraday’s 90 nm standard-cell library. The obtained results, when compared against the reference architecture, show that these novel architectures achieve significant improvements, namely, 25% in area and 35% in power consumption for the 128-EEA2 crypto-core, and even more important reductions are seen for the LSB coprocessor, that is, 36% in area and 50% in power consumption.

Efficient 45nm ASIC Architecture for Full-Search Free Intra Prediction in Real-Time H.264/AVC Decoder

The standard H.264/AVC Intra frame encoding process has several data dependent and computational intensive coding methodologies that limit the overall encoding speed. It causes not only a high degree of computational complexity but also an unacceptable delay especially for the real-time video applications. Based on DCT properties and spatial activity analysis, low power hardware architecture for high throughput Full-Search Free (FSF) Intra mode selection and direction prediction algorithm is proposed. The FSF Intra prediction Algorithm significantly reduces the computational complexity and the processing run-time required for the H.264/AVC Intra frame prediction process. The ASIC implementation for the proposed architecture is carried out and synthesizing results are obtained. The heavily tested 45nm ASIC design is able to achieve an operating frequency of 140 MHz while limiting the overall power consumption to 9.01 mW, which nominates our proposed FSF Intra prediction architecture for interactive real-time H.264/AVC mobile video decoders.

An iterative computation method for interpreting and extending an analytical battery model

Battery models are of great importance to develop portable computing systems, for whether the design of low power hardware architecture or the design of battery-aware scheduling policies. In this paper, we present a physically justified iterative computing method to illustrate the discharge, recovery and charge process of Li/Li-ion batteries. The discharge and recovery processes correspond well to an existing accurate analytical battery model: R-V-W’s analytical model, and thus interpret this model algorithmically. Our method can also extend R-V-W’s model easily to accommodate the charge process. The work will help the system designers to grasp the characteristics of R-V-W’s battery model and also, enable to predict the battery behavior in the charge process in a uniform way as the discharge process and the recovery process. Experiments are performed to show the accuracy of the extended model by comparing the predicted charge times with those derived from the DUALFOIL simulations. Various profiles with different combinations of battery modes were tested. The experimental results show that the extended battery model preserves high accuracy in predicting the charge behavior.

A COMPARATIVE ANALYSIS OF H.264 VIDEOCOMPRESSION STANDARD USING DIFFERENT ENTROPY CODING METHODS

In this paper, we present a comparative performance analysis of low power hardware architecture for real time implementation of context adaptive binary arithmetic coding algorithm and Context-based adaptive Variable Length Coding algorithm (CAVLC) used in H.264/ MPEG part 10 video coding standards. The video compression efficiency achieved in H.264 standard is not a result of any single feature but rather a combination of a number of encoding tools. CAVLC requires considerably more processing power to decode. The encoding process is simulated by MATLAB which compress the input video sequence and ensures better performance in video compression. The results that are obtained reveal better performance of both entropy coding methods.

Low-power design of direct conversion baseband DECT receiver

Portable terminals supporting the Digital Enhanced Cordless Telecommunications (DECT) standard have entered the world market in the last few years. For such devices low energy dissipation is of critical importance. In this paper, the design of a low-power fully digital baseband receiver that embodies innovative and conventional low-power optimizations is presented. The proposed baseband receiver complies with the DECT standard as far as digital modem functions are concerned. The developed energy-conscious, low complexity DECT demodulation algorithm and the low-power hardware architecture are described in a detailed manner.