Low-power Hardware Accelerator Research Articles

A Framework for Ultra Low-Power Hardware Accelerators Using NNs for Embedded Time Series Classification

In embedded applications that use neural networks (NNs) for classification tasks, it is important to not only minimize the power consumption of the NN calculation, but of the whole system. Optimization approaches for individual parts exist, such as quantization of the NN or analog calculation of arithmetic operations. However, there is no holistic approach for a complete embedded system design that is generic enough in the design process to be used for different applications, but specific in the hardware implementation to waste no energy for a given application. Therefore, we present a novel framework that allows an end-to-end ASIC implementation of a low-power hardware for time series classification using NNs. This includes a neural architecture search (NAS), which optimizes the NN configuration for accuracy and energy efficiency at the same time. This optimization targets a custom designed hardware architecture that is derived from the key properties of time series classification tasks. Additionally, a hardware generation tool is used that creates a complete system from the definition of the NN. This system uses local multi-level RRAM memory as weight and bias storage to avoid external memory access. Exploiting the non-volatility of these devices, such a system can use a power-down mode to save significant energy during the data acquisition process. Detection of atrial fibrillation (AFib) in electrocardiogram (ECG) data is used as an example for evaluation of the framework. It is shown that a reduction of more than 95% of the energy consumption compared to state-of-the-art solutions is achieved.

Real-time, High-resolution Depth Upsampling on Embedded Accelerators

High-resolution, low-latency apps in computer vision are ubiquitous in today’s world of mixed-reality devices. These innovations provide a platform that can leverage the improving technology of depth sensors and embedded accelerators to enable higher-resolution, lower-latency processing for 3D scenes using depth-upsampling algorithms. This research demonstrates that filter-based upsampling algorithms are feasible for mixed-reality apps using low-power hardware accelerators. The authors parallelized and evaluated a depth-upsampling algorithm on two different devices: a reconfigurable-logic FPGA embedded within a low-power SoC; and a fixed-logic embedded graphics processing unit. We demonstrate that both accelerators can meet the real-time requirements of 11 ms latency for mixed-reality apps. 1

Efficient neural network using pointwise convolution kernels with linear phase constraint

In current efficient convolutional neural networks, 1 × 1 convolution is widely used. However, the amount of computation and the number of parameters of 1 × 1 convolution layers account for a large part of these neural network models. In this paper, we propose to use linear-phase pointwise convolution kernels (LPPC kernels) to reduce the computational complexities and storage costs of these neural networks. We design four types of LPPC kernels based on the parity of the number of input channels and symmetry of the weights of the pointwise convolution kernel. Experimental results show that Type-I LPPC kernels can compress some popular networks better with a small reduction in accuracy than the other types of LPPC kernels. The LPPC kernels can be used as new 1 × 1 convolution kernels to design efficient neural network architectures in the future. Moreover, the LPPC kernels are friendly to low-power hardware accelerator design to achieve lower memory access cost and smaller model size.

Dynamically Adaptive Fast Motion Estimation Algorithm for HD Video

This paper presents a novel adaptive Fast Motion Estimation (FME) Algorithm, which reduces the number of search points, computational complexity and therefore lowering power consumption, while providing improved quality per watt in FME. The algorithm minimizes computation and storage and from there, power consumption, while trying to preserve quality as much as possible. It is very suitable for hardware implementation, as in a motion co-processor. The pervasiveness of mobile devices with HD video capabilities demands such low power hardware accelerators. The proposed algorithm is a novel method, that can identify the best search pattern within a given region of the HD video frame, based on its motion dynamics to achieve lower power video encoding. The goal is to achieve the best quality with the minimum number of search iterations. The reduced number of checks translates into power savings. The motivation of the presented algorithm is to learn the motion dynamics within a region from a small subset of blocks within that region and apply that knowledge to the remaining large set of blocks in the same region. This adaptiveness makes it robust with respect to the nature of the video. Thus it works equally well with more dynamic and with less dynamic video sequences. The results show that the proposed algorithm can reduce computations by about 4 times compared to other fixed search patterns algorithms, while staying within 1 dB of PSNR results. That equates to about 75% power savings at the expense of not more than 1 dB of PSNR quality loss.

Low-Power Hardware Accelerator for Detrending Measured Biopotential Data

Biopotential data measurement plays an important role in monitoring the body's physiological functions. It is affected by noise from various sources for different signals adversely affecting the ability to interpret them. The traditional methods of data detrending are either computationally inefficient, power-intensive, or have high latency. The maximum-mean-minimum (MaMeMi) filter reported for electrocardiogram (ECG) denoising is a computationally efficient algorithm. The MaMeMi filter response depends on two filter coefficients. In the real time, it is difficult to gauge the characteristics of the detected signal beforehand. In this article, we propose an adaptive-MaMeMi (AMaMeMi) filter, which adaptively computes the filter coefficients according to the properties of the input. We have used hardware-software codesign techniques for the optimized implementation of the AMaMeMi filter. The proposed hardware accelerator architecture for the AMaMeMi filter can be used in both adaptive and manual modes of operation. The hardware accelerator is tested for various biopotential signal detrendings, and the single hardware is capable of eliminating baseline wander from all considered measurements with less computational costs and low latency. We implemented the AMaMeMi filter on Xilinx Zynq-7000 system-on-chip (part number XCZ7020-CLG484-1) and statistically verified the results. The hardware accelerator implementation results provide a good correlation with MATLAB simulation results. The hardware accelerator implementation provides an average correlation of 0.9999, a normalized root-mean-square error of 0.0038, and a maximum signal-to-noise ratio (SNR) gain of 19 dB. The low computational complexity of the proposed architecture implies low-power consumption. It consumes 12 mW at 100-MHz clock and 0.7 mW at 500-Hz clock.

BioCNN: A Hardware Inference Engine for EEG-Based Emotion Detection

EEG-based emotion classifiers have the potential of significantly improving the social integration of patients suffering from neurological disorders such as Amyotrophic Lateral Sclerosis or the acute stages of Alzheimer's disease. Emotion classifiers have historically used software on general-purpose computers and operating under off-line conditions. Yet the wearability of such classifiers is a must if they are to enable the socialization of critical-care patients. Such wearability requires the use of low-power hardware accelerators that would enable near real-time classification and extended periods of operations. In this article, we architect, design, implement, and test a handcrafted, hardware Convolutional Neural Network, named BioCNN, optimized for EEG-based emotion detection and other bio-medical applications. The EEG signals are generated using a low-cost, off-the-shelf device, namely, Emotiv Epoc+, and then denoised and pre-processed ahead of their use by BioCNN. For training and testing, BioCNN uses three repositories of emotion classification datasets, including the publicly available DEAP and DREAMER datasets, along with an original dataset collected in-house from 5 healthy subjects using standard visual stimuli. A subject-specific training approach is used under TensorFlow to train BioCNN, which is implemented using the Digilent Atlys Board with a low-cost Spartan-6 FPGA. The experimental results show a competitive energy efficiency of 11 GOps/W, a throughput of 1.65 GOps that is in line with the real-time specification of a wearable device, and a latency of less than 1 ms, which is smaller than the 150 ms required for human interaction times. Its emotion inference accuracy is competitive with the top software-based emotion detectors.

Multiplexed stego path on reconfigurable hardware: A novel random approach

Information security, though having different areas of interest, is fairly specific and confined to secure digital data transmission. Currently, there are many data security techniques addressing various aspects of secured information sharing. Amongst those, one that is sufficiently epic, successful and challenging is steganography. This paper proposes a robust adaptive image steganography scheme titled the adaptive random inverted key LSB substitution technique, which combines steganography and cryptography to enhance the security of confidential data andimperceptibility of the stego object. FPGA implementation of the steganography technique provides massively parallel operations, perfect shielding against infectious attacks and ease of embedding as a low-power hardware accelerator in mobile computing systems. Hence, the proposed algorithm is implemented on a Cyclone II FPGA. The synthesized result demonstrates that the FPGA architecture yields a throughput of 441.38Mbps for data embedding and 914.29Mbps for data extraction.

Power Efficient High-Level Synthesis by Centralized and Fine-Grained Clock Gating

Nowadays, power is a primary concern in digital circuits and clock distribution networks are particularly a significant power consumer. Therefore, clock gating is an effective technique in saving dynamic power by reducing the switching activities. In this paper, we propose a centralized and fine-grained microarchitecture-level clock gating for low power hardware accelerators which are automatically designed by high-level synthesis (HLS) tool. The basic principium of our idea is not to use any extra computation for generating clock enabled signals and exploit exiting signals of finite state machine for controlling the datapath clock network. After determining the current state in finite state machine, clock sub-tree of current state is enabled and the other sub-trees are disabled with a slight increase in circuit area. Our approach is implemented within an HLS design flow for automatic low power hardware accelerator generation in application specific integrated circuit design. Experimental results are obtained on a set of representative benchmark programs. Depending on the circuit size and number of registers, it is shown that 47%–86% reduction in power dissipation is observed.