Low Power Full Adder Research Articles

CMOS full adder cells based on modified full swing restored complementary pass transistor logic for energy efficient high speed arithmetic applications

In modern Digital System design, adders are widely used in many applications including Microprocessors, Digital Signal Processors, Arithmetic Logic Units and digital signal processing. Power efficiency is an important key factor for any integrated circuits. By considering the importance of Full Adder (FA) cells, their power consumption may play significant role in overall power consumption. So designing a low-power full adder is important to achieve the high-performance computing. Swing restored technique is commonly used method to reduce the signal swing at the internal nodes and it helps to reduce the power consumption and improves the circuit's speed. This paper presents a novel hybrid full adder cell design using the modified swing restored technique and complementary pass transistor logic. The Full Adder circuit was implemented using Cadence Virtuoso tool on gptk 180nm CMOS process technology. The proposed full adder was compared with earlier reported circuits based on Delay, Power and PDP. The comparison shows that proposed circuit consumes less power with high performance. Also various process corners and noise immunity were analyzed to find the sensitivity of the circuit. Further an 8-bit Ripple Carry Adder was designed using the proposed full adder to verify the functionality in higher order bits. Simulations were performed and analysed using the Cadence Spectre.

Low Power and Fully Nonvolatile Full-Adder Based on STT-SHE-MRAM

Currently, static circuit power is becoming a major concern, dominating the total power consumption due to the scaling down of CMOS technology. The smaller sizes drastically affect the leakage current, which integrated circuit designers attempt to overcome this issue. Hence, several methods and technologies have been proposed to prevail this phenomenon. One of these methods is using memory structures in logic designs. A Hybrid MTJ/CMOS circuit is one of these promising techniques to design low-power nonvolatile circuits with power gating ability and low overhead for reconfigurable possibilities. In this paper, we have proposed a fully nonvolatile, low-power Full-Adder based on MTJs that uses the spin transfer torque method assisted by the spin hall effect. Simulation results of these designs by HSPICE show that they can work fast with low-power consumption compared to other state-of-the-art nonvolatile full-adders.

Design of Wallace tree multiplier circuit using high performance and low power full adder

The act of multiplying includes adding partial products repeatedly, and conventional multipliers call for many adders to perform partial product addition in higher order multiplication. A multiplier’s effectiveness and efficiency are evaluated using parameters such as speed, time delay, area, Power Delay Product (PDP), accuracy, and power consumption. In order to choose the optimum multiplier, this project is to evaluate various multipliers their performance metrics. Then, suggests employing a hybrid technology-based adder to improve the performance of the selected multiplier. The power consumption of the multiplier can be significantly reduced while maintaining the required accuracy by using a hybrid technology-based adder and low power full adders. This will allow multipliers to be used in low-power applications where power consumption is a major concern. To summarize, the goal of this project is to design and compare different multipliers using H-spice coding, as well as to improve the performance of the chosen. This project used 4x4 multiplier evaluation using 32nm technology.

Low Power Full Adders based on Proposed Hybrid and GDI Designs: A Novel Approach

Low Power Full Adders based on Proposed Hybrid and GDI Designs: A Novel Approach

DESIGN SPACE EXPLORATION OF LOW POWER FULL ADDER ACROSS MULTIPLE LOGIC STYLES AND PROCESS

The signal processing in digital domain becoming ubiquitous, a full adder circuit module has gained prominence for its optimization in terms of its speed, power dissipation, noise margin and area. Further, with the advent of mobile applications on electronic devices, low power has emerged as an overriding design criterion. The proposed work aims to explore the design space of a low power full adder circuit and the implications of logic styles on power-delay trade-offs. Further, the issues impacting the selection of process for design for a given application are addressed. A 1-bit full adder circuit in static CMOS logic style and hybrid logic style is designed and optimized for low-power by carrying out exhaustive simulations using the LT spice simulator in 65 nm and 45 nm standard process to explore their power envelope, before low power process becomes necessary for design. Low power designs are demonstrated and the trade-offs with speed and area are explored.

Design A Low Power and High Throughput 130nm Full Adder Utilising Exclusive-OR And Exclusive- NOR Gates

This literature illustrates the high speed and low power Full Adder (FADD) designs. This study relates to the composited structure of FADD design composed in one unit. In this the EXCL-OR/EXCL-NOR designs are used to design the FADD. Mostly concentrates on high speed standard FADD structure by combining the EXCL-OR/EXCL-NOR design in single unit. We implemented two composite structures of FADD through the full swing EXCL-OR/EXCL-NOR designs. And the EXCL-OR/EXCL-NOR design is done through pass transistor logic (PTL) and the same design projected on the composited FADD design. Such that the delay, area of the design, power requirement for the circuit gets optimized. The two composited FADD designs are compared and reduced the constraints of power requirement, area, delay and the power delay product (PDP). The simulated outcomes are verified through 130nnm CMOS mentor graphics tool.

Design a Low Power and High Speed 130nm Fulladder using Exclusive OR and Exclusive NOR Gates

This literature illustrates the high speed and low power Full Adder (FADD) designs. This study relates to the composited structure of FADD design composed in one unit. In this the EXCL-OR/EXCL-NOR designs are used to design the FADD. Mostly concentrates on high speed standard FADD structure by combining the EXCL-OR/EXCL-NOR design in single unit. We implemented two composite structures of FADD through the full swing EXCL-OR/EXCL-NOR designs. And the EXCL-OR/EXCL-NOR design is done through pass transistor logic (PTL) and the same design projected on the composited FADD design. Such that the delay, area of the design, power requirement for the circuit gets optimized. The two composited FADD designs are compared and reduced the constraints of power requirement, area, delay and the power delay product (PDP). The simulated outcomes are verified through 130nnm CMOS mentor graphics tool.

A novel ultra-low power 7T full adder design using mixed logic

The key point is to design and implementation of the full adder which provides high-speed, Power efficiency and leas area with good voltage swing”.Where the term ‘Novel’ indicates that If something is so new, genuine and original that it had never been seen, used or even thought of before, call it is considered as ‘novel’ and ‘Ultra low power’ indicates that with the minimal amount of system power is enough for performing the respective operation of its own. In this article, a new High Performance and low power full adder utilizing a distinctive design "Mixed Logic Design" is recommended in implementation. The mixed - logic design combines Modified Gate diffusion input (MGDI) Transmission Gate Logic (TGL), Static CMOS logic, Pass transistor logic(PTL )and various logics which requires the recommended circuit. Full adder is a digital circuit which performs the sum of bits. In many PC’s and various kinds of microprocessors, adders are utilized in the ALU. The traditional Complementary Metal Oxide Semiconductor (CMOS) Full adder consisting of 28-Transistors and is built on a traditional Complementary Metal Oxide Semiconductor structure. GDI technique is low power and high-speed design technique where it takes 10 T.Gate Diffusion Input is one of the circuit design logics which occupies less area, simulates with high speed and power-efficient technique. It entails less count of transistors as correlated to traditional Complementary Metal Oxide Semiconductor technology. But the disadvantage with Gate Diffusion Input technique is that it provides an output having poor logic swing after simulation. The Modified-Gate diffusion input (MGDI ) technique rectifies this issue by implementing FA with 8T.But we are implementing another alternative “Mixed logic design” (combining the GDI, CMOS, TGL, etc logics ) and designing the Circuit with least count of transistors and compare with other unique logics which helps them to simulate the circuit in a power-efficient way and time delay.

Low power CMOS full adder design with body biasing approach

In this paper, five different low power full adders using XOR/XNOR gates and multiplexer blocks with body biasing have been presented. In the first methodology, the adder depicts minimum power dissipation of 204.09μW and delay of 5.9849 ns. In the second, an improvement in power consumption has been reported at 128.92μW with delay of 5.9875 ns by using voltage biasing of two PMOS (P1 &P2) along with substrate biasing. In the third methodology, adder gives minimum power dissipation of 0.223nW with a delay of 5.2352 ns. Further, in fourth, it shows minimum power consumption of 0.199nW with a delay of 5.1002 ns and finally in fifth methodology, minimum power reduces to 0.192nW.Moreover, power delay product (PDP) results also have been compared for these methodologies. Comparisons have been made with earlier reported circuits and proposed circuits show better performance in terms of power consumption and delay.

Signal aware energy efficient approach for low power full adder design with adiabatic logic

Prolonged battery life is the major concern for modern low power electronic devices. Concentrating on this issue, in this paper a new structure of full adder has been proposed. Based on this architecture four new designs of low power full adder have been proposed. Two designs of proposed full adder i.e., A1 and A3 consist of four and three transistors based X-NOR gate respectively. Functionality of these two designs also verified with improved performance by employing diode free adiabatic logic (DFAL) in proposed adders, A2, and A4. Signal aware power efficient inverters have been used for proposed designs. Proposed adder designs are fast and consume less power as compared to the existing adders reported in literature. The proposed designs show a power delay product (PDP) of 0.041 fJ, 0.016 fJ, 0.054 fJ, and 0.047 fJ for adder A1, A2, A3 and, A4 respectively as compared to best reported double pass transistor full adder with 0.061 fJ. The proposed designs also perform well at stringent temperature, capacitance and, frequency conditions. These designs show satisfactory performance at low voltages whereas; the use of adiabatic logic makes these designs energy efficient for low power applications.

New MGDI-based full adder cells for energy-efficient applications

ABSTRACT In this paper, we present two new logic schemes to implement full adder cell using XOR-XNOR and NOR gates. Gate diffusion input (GDI) and modified GDI (MGDI) cells help to design low power circuits using less number of transistors. In this work, we design two new NOR gates based on MGDI cell. Then, using one of them and MGDI XOR-XNOR gates, two low-power and energy-efficient full adders which also meet full-swing property are proposed. The performance of our new full adders is evaluated and compared with some of the familiar full adders. Post-Layout simulations using Cadence Virtuoso tools in TSMC 0.18 μm CMOS process technology are carried out and the results show almost 24%–56% (22%–55%) and 36%–66% (28%–62%) improvements in the features power consumption and power-delay product (PDP), respectively. Also, full-swing property of our new adders are proved when they are subjected to all possible input combinations and transitions.

CNFET Based Low Power Full Adder Circuit for VLSI Applications

Background: The Adder is one of the most prominent building blocks in VLSI circuits and systems. Performance of such systems depends mostly on the performance of the adder cell. The scaling down of devices has been the driving force in technological advances. However, in CMOS technology performance of adder cell decreases as technology node scaled down to deep micron regime. Objective: With the growth of research, new device model has been proposed based on carbon nano tube field effect transistor (CNFET). Therefore, there is a need of full adder cell, which performs sufficiently well in CNFET as well as different CMOS technology nodes. Method: A new low power full adder cell has been proposed with a hybrid XOR/XNOR module by using CNFET, which is also compatible for the CMOS technology nodes. The performance of the adder cell is validated with HSPICE simulation in terms of power, delay and power delay product. It is observed that the proposed adder cell performs better than the CMOS, CPL, TGA, 10 T, 14 T, 24 T, HSPC and Hybrid_FA adder cells. The CNFET full adder is designed in 32 nm CNFET model and to appraise its compatibility with Bulk-Si CMOS technology, 90 nm and 32 nm CMOS technology node is used. Conclusion: The proposed adder is very much suitable for both CMOS and CNFET technology based circuits and systems. To validate the result, simulation has been carried out with Synopsis tool. This full adder will definitely dominate other full adder cells at various technology nodes for VLSI applications.

HIGH SPEED ADDER USING GDI TECHNIQUE

Full adder is an important component for designing a processor. As the complexity of the circuit increases, the speed of operation becomes a major concern. Nowadays there are various architectures that exist for full adders. In this paper we will discuss about designing a low power and high speed full adder using Gate Diffusion Input technique. GDI is one of the present day methods through which one can design logical circuits. This technique will reduce power consumption, propagation delay, and area of digital circuits as well as maintain low complexity of logic design. The performance of the proposed design is compared with the contemporary full adder designs.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

Carbon Nanotube Field Effect Transistor-Based Hybrid Full Adders Using Gate-Diffusion Input Structure

Scaling down the size of transistor in the nanoscale reduces the power supply voltage, as a result, the design of high-performance nano-circuit at low voltage has been considered. Most of digital circuits are composed of different components which determine the performance of the entire digital circuits. With the improvement of these components, the digital circuits can be optimized. One of these components is full adder for which various structures have been proposed to improve its performance, among them the two novel full adder structures are based on Gate-Diffusion Input (GDI) structure and half-classical XOR/XNOR logic (SEMI XOR/XNOR) modules. In this paper, Carbon Nanotube Field Effect Transistor (CNTFET)-based low power full adders by using SEMI XOR logic style and GDI structure are presented. Due to the incomparable thermal and mechanical properties of the CNTFET, it can be the first alternative to substitute the metal oxide field effect transistors (MOSFET). The digital circuits have the better performance based on CNTFET. Therefore, the three proposed full adders in this paper are designed based on CNTFET technology with many merits, such as low power dissipation, less energy delay product (EDP), and high speed at various supply voltages, frequencies, temperatures, load capacitors, and the number of tubes. Moreover, these proposed full adders occupy the minimum area consumption and have better performance in comparison with previous standard full adders. All simulations are done by using the Synopsys HSPICE simulator in 32 nm-CNTFET technology and layout of all full adder circuits are presented on Electric.

A body bias technique for low power full adder using XOR gate and pseudo NMOS transistor

Power dissipation is a major issue in digital circuit design. As technology into developed into range, power and delay becomes vital nanometer parameters to ameliorate the performance of the circuit. To minimize the power consumption many low power techniques such as MTCMOS, stacking, body biasing techniques have been reported. In this paper, a new pseudo NMOS adder circuits have presented. It has designed using transmission gate and body bias technique. Simulation has been accomplished by using SPICE tool. The simulation result show the validity of the proposed techniques is reduces power dissipation from 0.367 mW to 0.267 mW and PDP reduced from 19.311pJ to 13.311pJ. Overall improvement of 29% in power consumption and 30% in PDP has obtained.

Theory of Expansion Boolean Algebra and Its Applications in CMOS VLSI Digital Systems

Based on the relationship between circuits (systems) and the signals in the circuits (systems), the theory of expansion Boolean algebra is presented in this paper. Static complementary logic circuits and static pass transistors logic circuits have been used to implement the high-speed and low-power-consumption cells circuits in CMOS VLSI systems. It is important to study the extraction method of logic expressions for these types of circuits. By analyzing the operations principles of MOS transistors in CMOS circuits, the theory of expansion Boolean algebra of CMOS logical circuits is presented. Based on the algebraic theory, a method of extracting the logic expressions from the two types of CMOS logical circuits is derived. On the basis of the method, a switch-level design method of CMOS logic circuits based on the algebra theory is presented, and the design method is used to design the high-speed and low-power full adder cells in CMOS VLSI systems. By the results of the simulation experiments, it is shown that the pass transistors and transmission gates hybrid CMOS full adder circuits proposed in this paper have a lower power-delay product by comparison with the full adder circuits designed by using other methods.

Designing energy-efficient imprecise adders with multi-bit approximation

Since early 2000s, achieving significant energy-efficiency for CMOS VLSI circuit design has become more difficult. Approximate computing is a hopeful solution for enhancing power-efficiency in error-tolerant applications. In such systems, adders play an essential role and mainly contribute to the system's total power and area consumption. Many proposals have been introduced in the literature that build large adders while using novel low power full adder structure as its building blocks. However, single-bit structure approximation, only limits the design space of approximate adders. And leads to a poor trade-off between accuracy and power dissipation. This paper proposes a novel approach for design of multi-bit adders, based on three novel approximate 2-bit adder circuits. Simulation results demonstrates that the proposed adders consume less area and power than the state-of-the-art approximate adders. Up to 80% power improvements are attainable for the proposed designs as compared with the baseline adders.

HIGH SPEED AND LOW POWER GDI BASED FULL ADDER

Full adder is one of the fundamental digital block in the many electronic circuits. As the day by day scaling down the technology(Deep-sub micron level) power consumption becomes one of the primary concern for any portable electronic devices. In this paper our main motto is to design and implement the low power full swing full adder, using GDI (Gate Diffusion input )technique. Simulated full swing GDI based adder using the cadence virtuoso in 180nm technology. and also we conducted the a comprehensive study on different types of full adders and their performances with respect to SERF and 28 T circuits respectively.

Fully Nonvolatile and Low Power Full Adder Based on Spin Transfer Torque Magnetic Tunnel Junction With Spin-Hall Effect Assistance

As technology node scales down below 90 nm, the conventional complementary metal oxide semiconductor (CMOS) logic circuits suffer from various problems such as high standby power due to increase in leakage current. Spintronic devices based on magnetic tunnel junction (MTJ) is one of the most promising technology candidates for the future of the digital circuits. MTJ-based logic circuits can offer nonvolatility, high endurance, high density, low standby power dissipation, and 3-D integration capability with the CMOS technology. In recent years, several full-adder circuits are proposed based on MTJs that are not fully nonvolatile since they use MTJs to store only one of their inputs. This paper proposes a fully nonvolatile magnetic full-adder (MFA) circuit offering the capability of power gating with no loss of data. The proposed circuit stores all the inputs in MTJs using the spin-transfer torque (STT) method assisted by the spin-Hall effect (SHE). Thanks to the SHE assistance, delay and power consumption of the MTJ switching are reduced significantly. Moreover, as a result of lower write current, the endurance of the oxide barrier can be increased. Using a three-terminal SHE–STT–MTJ model and a 45 nm CMOS SPICE model, we simulated and validated the functionality of our design and compared it with some recent previous MFAs. Simulation results reveal that the proposed MFA offers considerable superiorities over the recent counterparts.