Low-power Field-programmable Gate Array Research Articles

The Nature-Inspired BASIS Feature Descriptor for UAV Imagery and Its Hardware Implementation

This paper presents a feature descriptor well suited for limited-resource applications such as an unmanned aerial vehicle embedded systems, small microprocessors, and small low-power field programmable gate array (FPGA) fabric. The basis sparse-coding inspired similarity (BASIS) descriptor utilizes sparse coding to create dictionary images that model the regions in the human visual cortex. Due to the reduced amount of computation required for computing BASIS descriptors, reduced descriptor size, and the ability to create the descriptors without the use of a floating point, this approach is an excellent candidate for FPGA hardware implementation. The bit-level-accurate BASIS descriptor was tested on a dataset of real aerial images with the task of calculating a frame-to-frame homography and compared to software versions of scale-invariant feature transform (SIFT) and speeded-up robust features (SURF). Experimental results show that the BASIS descriptor outperforms SIFT and performs comparably to SURF on frame-to-frame aerial feature point matching. BASIS descriptors require less memory storage than other descriptors and can be computed entirely in hardware, allowing the descriptor to operate at real-time frame rates on a low-power embedded platform such as an FPGA.

An Energy-Efficient Memristive Threshold Logic Circuit

Researchers have claimed that the memristor, the fourth fundamental circuit element, can be used for computing. In this work, we utilize memristors as weights in the realization of low-power Field Programmable Gate Arrays (FPGAs) using threshold logic which is necessary not only for low power embedded systems, but also realizing biological applications using threshold logic. Boolean functions, which are subsets of threshold functions, can be implemented using the proposed Memristive Threshold Logic (MTL) gate, whose functionality can be configured by changing the weights (memristance). A CAD framework is also developed to map the weights of a threshold gate to corresponding memristance values and synthesize logic circuits using MTL gates. Performance of the MTL gates at the circuit and logic levels is also evaluated using this CAD framework using ISCAS-85 combinational benchmarking circuits. This work also provides solutions based on device options and refreshing memristance, against drift in memristance, which can be a potential problem during operation. Comparisons with the existing CMOS look-up-table (LUT) and capacitor threshold logic (CTL) gates show that MTL gates exhibit less energy-delay product by at least 90 percent.

FPGA-Based Adaptive Speckle Suppression Filter for Underwater Imaging Sonar

Underwater forward-looking imaging sonar (FLS) is widely used on stationary and moving platforms to overcome underwater visibility problems. The SONAR images are perturbed by a multiplicative noise called speckle, due to the coherent nature of the scattering phenomenon. Speckle reduction filters are necessary to optimize the images' exploitation procedures. The results of speckle filters may vary from one sensor and one wavelength to another; therefore, no generic de-speckling algorithm exists. Several studies have been carried out on speckle noise suppression on sidescan sonar, but the problem of speckle noise suppression for FLS has not yet been covered. A comparison of the most used classical speckle suppression filters as well as advanced wavelet-based ones was carried out. The Frost filter was found to be the most adequate for FLS data, but also the most computationally complex and not suitable for real-time processing. Two novel architectures for real-time and low-power field-programmable gate array (FPGA) implementation of the Frost speckle filter for underwater imaging sonar are presented. The proposed architectures have superior performance and power efficiency compared to standard software implementation.

Editorial

Radiation caused by radiation sources due to ionization in the form of alpha, beta, gamma, X-ray and neutron radiations is harmful to human health. Multi-Channel Analyzers (MCAs) are incorporated in nuclear instruments for various applications like Isotope identifiers, Alpha/Gamma spectroscopy and liquid scintillators etc., that demand wide resolutions. Analog signal which is detected by the detector from radiation source is converted into digital using Analog-to-Digital Converter (ADC). Trapezoidal shaping is done by the Digital Signal Processor (DSP) using the proposed algorithms. This work targets the design and implementation of Digital Multi Channel Analyzer implemented on FPGA that can be used in nuclear spectroscopy instruments. The MCA system is designed by using trapezoidal recursive algorithm with the help of Lower Level Discriminator (LLD) and Upper Level Discriminator (ULD) detection using peak detection. The height of the pulse is the proportional to the energy of the particle which is used for peak detection. The peak detection data is counted, and histograms are generated for data analysis. This system is designed and realized by using Verilog Hardware Description Language (HDL) with low power and high profile SmartFusion2 FPGA SoC that can be used in nuclear spectroscopy instruments. The peak detection and counting are done by the modules developed using Hardware Description language (HDL) aiming the target device to be the Smart Fusion 2 Field Programmable Gate Array (FPGA) which has in-built Digital Signal Processor (DSP).

A Low-Power FPGA Based on Autonomous Fine-Grain Power Gating

This paper presents a field-programmable gate array (FPGA) based on lookup table level fine-grain power gating with small overheads. The power gating technique implemented in the proposed architecture can directly detect the activity of each look-up-table easily by exploiting features of asynchronous architectures. Moreover, detecting the data arrival in advance prevents the delay increase for waking-up and the power consumption of unnecessary power switching. Since the power gating technique has small overheads, the granularity size of a power-gated domain is as fine as a single two-input and one-output lookup table. The proposed FPGA is fabricated using the ASPLA 90-nm CMOS process with dual threshold voltages. We use an image processing application called “template matching” for evaluation. Since the proposed FPGA is suitable for processing where the workload changes dynamically, an adaptive algorithm where a small computational kernel is employed. Compared to a synchronous FPGA and an asynchronous FPGA without power gating, the power consumption is reduced respectively by 38% and 15% at 85°C.

A Gigabit per second read-out system for Medipix Quads

A system to read-out images from four photon-counting Medipix chips at one Gigabit per second has been constructed in a bilateral collaboration between Nikhef and PANalytical. The system consists of two printed circuit boards. One board supports the four Medipix readout ASICs, flip-chipped to a single pixellized semiconducting sensor on top. This board is mounted perpendicular on the Relaxd read-out board. This Relaxd board supplies the necessary voltages to the Medipix readout ASICs, controls all signals to and from these chips via a low-power Field Programmable Gate Array (FPGA, Lattice SC series) and communicates with a PC through a standard one Gigabit per second Ethernet connection (GbE). The T-shaped mechanical topology allows multiple modules to be mounted adjacent to each other in all directions (2D tiling) and to minimise the insensitive area between separate Relaxd modules. An overview of the system layout and the functionality is presented as well as the first test results.

A Routing Approach to Reduce Glitches in Low Power FPGAs

This paper presents a novel approach to reduce dynamic power in field-programmable gate arrays (FPGAs) by reducing glitches during routing. It finds alternative routes for early-arriving signals so that signal arrival times at look-up tables are aligned. We developed an efficient algorithm to find routes with target delays and then built a glitch-aware router aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 27% reduction in glitch power is achieved, which translates into an 11% reduction in dynamic power, compared to the glitch-unaware versatile place and route's router.

Real-Time Hand-Held Ultrasound Medical-Imaging Device Based on a New Digital Quadrature Demodulation Processor

A fully hardware-based real-time digital wideband quadrature demodulation processor based on the Hilbert transform is proposed to process ultrasound radio frequency signals. The presented architecture combines 2 finite impulse response (FIR) filters to process in-phase and quadrature signals and includes a piecewise linear approximation architecture that performs the required square root operations. The proposed implementation enables flexibility to support different transducers with its ability to load on-the-fly different FIR filter coefficient sets. The complexity and accuracy of the demodulator processor are analyzed with simulated RF data; a normalized residual sum-of-squares cost function is used for comparison with the Matlab Hilbert function. Three implementations are integrated into a hand-held ultrasound system for experimental accuracy and performance evaluation. Real-time images were acquired from a reference phantom, demonstrating the feasibility of using the presented architecture to perform real-time digital quadrature demodulation of ultrasonic signal echoes. Experimental results show that the implementation, using only 2942 slices and 3 dedicated digital multipliers of a low-cost and low-power field-programmable gate array (FPGA) is accurate relative to a comparable software- based system; axial and lateral resolution of 1 mm and 2 mm, respectively, were obtained with a 12-mm piezoelectric transducer without postprocessing. Because the processing and sampling rates are the same, high-frequency ultrasound signals can be processed as well. For a 15-frame-per-second display, the hand-held ultrasonic imaging-processing core (FPGA, memory) requires only 45 mW (dynamic) when using a 5-MHz single-element piezoelectric transducer.

Power-Efficient Clock/Data Distribution Technique for Polyphase Comb Filter in Digital Receivers

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A power-efficient clock/data distribution technique for the input registers of the polyphase comb decimation filter is presented. A general form of the proposed technique is developed with respect to the decimation factor. Both proposed and conventional comb filters are implemented using Xilinx Spartan3 low-power field-programmable gate array family. The implementation results show that applying the proposed technique reduces the dynamic power consumption of the second- and third-order polyphase comb filters up to 62.87% and 57.6%, respectively, depending on the decimation factor and the number of quantizer bits. For a particular power consumption, a higher input sampling rate can be utilized by applying the proposed technique. Consequently, the signal-to-noise ratio of a second-order <formula formulatype="inline"><tex Notation="TeX">$\Sigma\Delta$</tex></formula> modulator is increased using second- and third-order modified filters by 21.6 and 20.5 dB, respectively, depending on the decimation factor and the number of quantizer bits. </para>

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

A 12-Gb/s DEMUX Implemented With SiGe High-Speed FPGA Circuits

A 7-12-Gb/s demultiplexer implemented with circuits for a high-speed field-programmable gate array (FPGA) is introduced in this paper. Since the first FPGA was released by Xilinx in 1985, FPGAs have become denser and more powerful. The first FPGA that operates in the microwave range was designed in 2000. Various methods, such as a new basic cell structure and multimode routing, are used to make that design faster and less power consuming. Sequential logic functions are analyzed and tested in this paper with a DEMUX implementation using these high-speed FPGA circuits. A chip measurement has shown that the FPGA can operate at a 12-GHz system clock when configured to perform sequential logic. A DEMUX that operates at 12 Gb/s is used here to demonstrate the potential for high-performance and low-power FPGA features.

A 90-nm Low-Power FPGA for Battery-Powered Applications

Programmable logic devices such as field-programmable gate arrays (FPGAs) are useful for a wide range of applications. However, FPGAs are not commonly used in battery-powered applications because they consume more power than application-specified integrated circuits and lack power management features. In this paper, we describe the design and implementation of Pika, a low-power FPGA core targeting battery-powered applications. Our design is based on a commercial low-cost FPGA and achieves substantial power savings through a series of power optimizations. The resulting architecture is compatible with existing commercial design tools. The implementation is done in a 90-nm triple-oxide CMOS process. Compared to the baseline design, Pika consumes 46% less active power and 99% less standby power. Furthermore, it retains circuit and configuration state during standby mode and wakes up from standby mode in approximately 100 ns

Reconfigurable embedded MAC core design for low-power coarse-grain FPGA

A reconfigurable multiplier design for low-power field programmable gate arrays (FPGAs) is presented. Power consumption reduction is achieved through varying the depth of pipeline of the multiplier. The multiplier incorporates a capability of configuring itself dynamically, thus, is suitable for FPGA type of design.