Low-power Digital Signal Processor Research Articles

Revolutionizing Digital Signal Filters: A Breakthrough in Low-Power Multipliers

In the ever-evolving landscape of digital signal processing technology, the ubiquitous presence of digital signal filters has become a cornerstone across a myriad of domains including radar, computing, and communications. Amidst the relentless pursuit of more efficient solutions, a pivotal development emerges - the creation of a low-power multiplier tailored explicitly for digital signal filters. This innovation hinges upon the judicious selection of a carry-lookahead adder as a fundamental building block within the multiplier, ushering in enhancements that ripple through its operation. This transformative leap doesn't halt at the component level; it extends its reach further by delving into meticulous optimizations encompassing logic gate dimensions and set voltage parameters. These refinements, executed with precision, culminate in a substantial reduction in the energy consumption of the multiplier, effectively setting it apart from conventional counterparts. Remarkably, these advances don't merely remain theoretical; they find their footing in practical industry applications, thus birthing a new era in the creation of low-power digital signal filters. The profound implications of this development reverberate far and wide, notably benefiting the realm of low-power digital signal processing and its associated applications.

Recent Advances in Low-Power Digital Signal Processing Technologies for Data Center Applications

Recent Advances in Low-Power Digital Signal Processing Technologies for Data Center Applications

A Fully Integrated Sensor-Brain–Machine Interface System for Restoring Somatosensation

Sensory feedback is critical to the performance of neural prostheses that restore movement control after neurological injury. Recent advances in direct neural control of paralyzed arms present new requirements for miniaturized, low-power sensor systems. To address this challenge, we developed a fully-integrated wireless sensor-brain-machine interface (SBMI) system for communicating key somatosensory signals, fingertip forces and limb joint angles, to the brain. The system consists of a tactile force sensor, an electrogoniometer, and a neural interface. The tactile force sensor features a novel optical waveguide on CMOS design for sensing. The electrogoniometer integrates an ultra low-power digital signal processor (DSP) for real-time joint angle measurement. The neural interface enables bidirectional neural stimulation and recording. Innovative designs of sensors and sensing interfaces, analog-to-digital converters (ADC) and ultra wide-band (UWB) wireless transceivers have been developed. The prototypes have been fabricated in 180nm standard CMOS technology and tested on the bench and in vivo. The developed system provides a novel solution for providing somatosensory feedback to next-generation neural prostheses.

Estimating Reliability of Signal Quality of Physiological Data from Data Statistics Itself for Real-time Wearables.

Artificial intelligence (AI) algorithms including machine and deep learning relies on proper data for classification and subsequent action. However, real-time unsupervised streaming data might not be reliable, which can lead to reduced accuracy or high error rates. Estimating reliability of signals, such as from wearable sensors for disease monitoring, is thus important but challenging since signals can be noisy and vulnerable to artifacts. In this paper, we propose a novel "Data Reliability Metric (DReM)" and demonstrate the proof-of-concept with two bio signals: electrocardiogram (ECG) and photoplethysmogram (PPG). We explored various statistical features and developed Artificial Neural Network (ANN), Random Forest (RF) and Support Vector Machine (SVM) models to autonomously classify good quality signals from the bad quality signals. Our results demonstrate the performance of the classification with a cross-validation accuracy of 99.7%, sensitivity of 100%, precision of 97% and F-score of 96%. This work demonstrates the potential of DReM to objectively and automatically estimate signal quality in unsupervised real-time settings with low computational requirement suitable for low-power digital signal processing techniques on wearables.

An Energy Metering and Measurement SoC With a Novel Low-Power DSP Architecture

This paper presents an energy metering and measurement system-on-a-chip (SoC) with a novel low-power digital signal processor (DSP) architecture. The Cotex-M0-based SoC can measure electricity signals and meter active and reactive energy. It can also monitor the grid by directly accessing and analyzing the waveforms. The measurement and metering algorithms are implemented in a novel DSP architecture with a dedicated reduced instruction set. The filter coefficients and its operating frequency in the default program of DSP can be reprogrammed independently. It can be applied in different applications where demands for metering bandwidth and response time are different. The DSP program can also be reprogrammed by the software if the default program is not desired. The SoC is implemented in a 0.11- ${\mu }\text{m}$ CMOS process. It achieves active and reactive energy metering accuracy of 0.1% with a dynamic range of 5000:1. The analog power supply is 3.3 V and the digital power supply is 1.8 V. The total power consumption of the SoC is ca 17.63 mW with the DSP consuming ca 1.0 mW. Compared with other commercial metering and measurement SoCs, the presented SoC achieves higher metering accuracy and lower power consumption. It is currently in production.

A 256 pixel, 21.6 μW infrared gesture recognition processor for smart devices

This paper presents a low-power digital signal processor for gesture detection using infrared (IR) sensors. IR compatible detecting algorithms are introduced to reduce power consumption and provide accurate detections for various types of gestures including sweeping in 8 directions, zooming in/out and a unique wake-up gesture. To further reduce the power, the proposed algorithm is capable of setting the processor into idle mode when there is no motion and resume active mode upon wake-up request. Test chips were fabricated in a 65 nm commercial TSMC process and occupy an area of 580 μm × 580 μm. Measurement results taking input from a 16 × 16 Heiman IR sensor array show that the proposed gesture recognition processor is able to detect correct gestures at 100 MHz maximum clock frequency. Under normal working condition, the processor consumes 21.6 μW in active mode and 7.2 μW in idle mode while processing 8-bit 16 × 16 input data array at 30 fps.

A Fast Converging Normalization Unit for Stochastic Computing

Stochastic computing is a promising technology for low hardware cost and low power digital signal processing (DSP) systems. However, the quite slow convergence of stochastic normalization leads to low throughput of stochastic computing based DSP systems. In this brief, we propose a fast converging stochastic normalization unit based on joint probability tracking (JPT) method, which operates modified probability tracking on random bit streams to perform the normalization. Simulation results show that the convergence speed of the JPT scheme is as 3.5 times as that of existing methods. According to the synthesis results on 65-nm CMOS technology, the JPT scheme achieves higher (2.8 times) hardware efficiency gains with respect to the existing stochastic computing-based schemes.

An Efficient DSP–FPGA-Based Implementation of Hybrid PWM for Electric Rail Traction Induction Motor Control

Low switching frequency is always used in an electric rail traction induction motor control system, in order to reduce switching losses and increase system reliability. But under low switching frequency, the conventional single pulse width modulation (PWM) technique for the whole speed region will produce a large number of harmonic components, which in turn cause motor heating, torque ripple, and other adverse effects. In this paper, a hybrid PWM technique formed by merging carrier-based asynchronous and synchronous modulation and optimal synchronous modulation is proposed to achieve low losses and total harmonics based on very low switching frequency. A simple low-cost and low-power digital signal processor (DSP) and field programmable gate array (FPGA) hybrid hardware structure is then adopted for implementing the technique, which fully utilizes advantages and resources of each processor. Total harmonic distortion of the system can hence be reduced by operating with the high-precision hybrid PWM, while not compromising the multirate and multitask processing requirements of traction control. Detailed implementations in both DSP and FPGA with high accuracy, low usage of resources, and computational burden are then described, focusing particularly at the smooth transitions among different PWM schemes. Simulations and experiments are eventually performed with results captured for validating the presented hybrid PWM technique.

Opportunistic and Context-Aware Affect Sensing on Smartphones

Opportunistic affect sensing offers unprecedented potential for capturing spontaneous affect ubiquitously, obviating biases inherent in the laboratory setting. Facial expression and voice are two major affective displays, however most affect sensing systems on smartphone avoid them due to extensive power requirement. Encouragingly, due to the recent advent of low-power DSP (Digital Signal Processing) co-processor and GPU (Graphics Processing Unit) technology, audio and video sensing are becoming more feasible. To properly evaluate opportunistically captured facial expression and voice, contextual information about the dynamic audio-visual stimuli needs to be inferred. This paper discusses recent advances of affect sensing on the smartphone and identifies the key barriers and potential solutions of implementing opportunistic and context-aware affect sensing on smartphone platforms.

Noise reduction of speech signals using time-varying and multi-band adaptive gain control for smart digital hearing protectors

In this paper, a single-channel speech enhancement algorithm based on non-linear and multi-band Adaptive Gain Control (AGC) is proposed. The algorithm requires neither Signal-to-Noise Ratio (SNR) nor noise parameters estimation. It reduces the background noise in the temporal domain rather than the spectral domain using a non-linear and automatically adjustable gain function for multi-band AGC. The gain function varies in time and is deduced from the temporal envelope of each frequency band to highly compress the frequency regions where noise is present and lightly compress the frequency regions where speech is present. Objective evaluation using the PESQ (Perceptual Evaluation of Speech Quality) metric shows that the proposed algorithm performs better than three benchmarks, namely: the spectral subtraction, the Wiener filter based on a priori SNR estimation and a band-pass modulation filtering algorithm. In addition, blind subjective tests show that the proposed algorithm introduces less musical noise compared to the benchmark algorithms and was preferred 78.8% of the time in terms of signal quality. The proposed algorithm is implemented in a miniature low power digital signal processor to validate its feasibility and complexity for smart hearing protection in noisy environments.

Reliable Low Power FIR Filter using Vedic Multiplier

Recent trends in mobile computing and multimedia application demand low power digital signal processing systems (DSP). The most important block in any DSP system is a finite impulse response (FIR) filter. Here a reliable low power FIR filter is designed using Vedic multipliers which specifically perform addition and shifting operation. The addition is done using full adder with 9 transistors which use only 3 transistor XOR gate. A four tap FIR filter was implemented in microwind 2 electronic design automation tool using CMOS 90nm technology. In the proposed design the power consumption is reduced by 23% and delay has been reduced by 44% when compared with the existing FIR filters.

Real-time blind audio source separation: performance assessment on an advanced digital signal processor

Many on-line blind audio source separation (BASS) algorithms have been presented so far to the scientific community, but only a few of them have been evaluated in terms of their real-time performance. In this paper we consider a well-established BASS method (oriented to voices separation) evaluating its performance in terms of separation quality allowed by a real-time embedded computing implementation, also considering novel and state-of-the-art improvements to the it. To this aim, the algorithm has been implemented and ported for real-time execution onto an advanced low-power digital signal processor targeted for complex-domain applications. The optimized embedded implementation is able to perform up to five iterations of the gradient for any input frame of data, achieving good separation levels (up to 11.8 dB of signal to interference ratio on custom recording in real environments). The proposed solution doubles the performance of a C-optimized version running on a traditional PC processor, achieving a better separation result with lower power requirements.

Hyperspectral Unmixing on Multicore DSPs: Trading Off Performance for Energy

Wider coverage of observation missions will increase onboard power restrictions while, at the same time, pose higher demands from the perspective of processing time, thus asking for the exploration of novel high-performance and low-power processing architectures. In this paper, we analyze the acceleration of spectral unmixing, a key technique to process hyperspectral images, on multicore architectures. To meet onboard processing restrictions, we employ a low-power Digital Signal Processor (DSP), comparing processing time and energy consumption with those of a representative set of commodity architectures. We demonstrate that DSPs offer a fair balance between ease of programming, performance, and energy consumption, resulting in a highly appealing platform to meet the restrictions of current missions if onboard processing is required.

Low-power wearable respiratory sound sensing.

Building upon the findings from the field of automated recognition of respiratory sound patterns, we propose a wearable wireless sensor implementing on-board respiratory sound acquisition and classification, to enable continuous monitoring of symptoms, such as asthmatic wheezing. Low-power consumption of such a sensor is required in order to achieve long autonomy. Considering that the power consumption of its radio is kept minimal if transmitting only upon (rare) occurrences of wheezing, we focus on optimizing the power consumption of the digital signal processor (DSP). Based on a comprehensive review of asthmatic wheeze detection algorithms, we analyze the computational complexity of common features drawn from short-time Fourier transform (STFT) and decision tree classification. Four algorithms were implemented on a low-power TMS320C5505 DSP. Their classification accuracies were evaluated on a dataset of prerecorded respiratory sounds in two operating scenarios of different detection fidelities. The execution times of all algorithms were measured. The best classification accuracy of over 92%, while occupying only 2.6% of the DSP's processing time, is obtained for the algorithm featuring the time-frequency tracking of shapes of crests originating from wheezing, with spectral features modeled using energy.

Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings

This paper presents and analyzes a fully digital instruction-cycle-based dynamic voltage scaling (iDVS) power management strategy for low-power processor designs. The proposed iDVS technique is fully compatible with conventional DVS scheduler algorithms. An additional computer aided design-based design flow was embedded in a standard cell library to implement the iDVS-based processor in highly integrated system-on-a-chip applications. The lattice asynchronous self-timed control digital low-dropout regulator with swift response and low quiescent current was also utilized to improve iDVS voltage transition response. Results show that the iDVS-based processor with the proposed adaptive instruction cycle control scheme can efficiently perform millions of instructions per second during iDVS transition. The iDVS-based digital signal processor chip was implemented in a HH-NEC 0.18-μm standard complementary metal-oxide semiconductor. Measurement results show that the voltage tracking speed with 11.6 V/μs saved 53% power.

Intelligent Monitoring of Multistory Buildings under Unknown Earthquake Excitation by a Wireless Sensor Network

It is necessary to investigate techniques for monitoring structures under unknown earthquakes. For this purpose, an algorithm is proposed in this paper for the identification of structures and excitation of multi-story shear buildings with limited measurements of structural responses. The equation of motion of a multi-story shear building under ground motion is established in the absolute co-ordinate system, while the multi-story building is decomposed into substructures. A novel two-step Kalman estimator approach, which is not available in the previous literature, is proposed for the identification substructures and unknown ground motion with less computational effort. Then, for the purpose of intelligent structural monitoring, a new wireless sensor network is developed in this paper. The designed wireless sensor network has a two-level cluster-tree architecture. Hardware designs of the sensor unit and the cluster head are presented; especially the cluster head contains a low power digital signal processor with strong computing capacity. Thus, the wireless sensor network has the unique feature offers distributed computing at group level. Finally, the proposed algorithm is embedded into the wireless sensor network for intelligent structural monitoring and an experimental test shows the technique is effective for intelligent monitoring of multi-story buildings under unknown earthquakes.

Extensible Recognition of Algorithmic Patterns in DSP Programs for Automatic Parallelization

We introduce an extensible knowledge based tool for idiom (pattern) recognition in DSP (digital signal processing) programs. Our tool utilizes functionality provided by the Cetus compiler infrastructure for detecting certain computation patterns that frequently occur in DSP code. We focus on recognizing patterns for for-loops and statements in their bodies as these often are the performance critical constructs in DSP applications for which replacement by highly optimized, target-specific parallel algorithms will be most profitable. For better structuring and efficiency of pattern recognition, we classify patterns by different levels of complexity such that patterns in higher levels are defined in terms of lower level patterns. The tool works statically on the intermediate representation. For better extensibility and abstraction, most of the structural part of recognition rules is specified in XML form to separate the tool implementation from the pattern specifications. Information about detected patterns will later be used for optimized code generation by local algorithm replacement e.g. for the low-power high-throughput multicore DSP architecture ePUMA.

Performance Analysis of Parallel FIR Digital Filter using VHDL

With the continuing trends to reduce the chip size and integrates multichip solution into a single chip solution it is important to limit the silicon area required to implement parallel FIR digital filter in VLSI implementation. The Need for high performance and low power digital signal processing is getting increased. Finite Impulse Response (FIR) filters are one of the most widely used fundamental devices performed in DSP system. This paper presents the performance analysis of parallel FIR digital filter, In this paper, Traditional FIR filter structure and FFA based FIR filter structure and symmetric convolution based FFA FIR filter are designed for 2-parallel filter (2*2). These entire filter structures are designed based on Carry Save Adder (CSA) and Ripple Carry Adder (RCA).Exchanging multipliers with adder is advantageous because adders weight less then multipliers in terms of silicon area. The performance of parallel FIR filter structure based on Ripple Carry Adder and Carry Save Adder will be compared.

A Low-Power DSP for Wireless Communications

This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture-Signal processing On Demand Architecture (SODA)-which is a four-processor, 32-lane SIMD machine that was optimized for WCDMA 2 Mbps and IEEE 802.11a. SODA has several shortcomings including large register file power, wasted cycles for data alignment, etc., and cannot satisfy the higher throughput and lower power requirements of emerging standards. We propose SODA-II, which addresses these problems by deploying the following schemes: operation chaining, pipelined execution of SIMD units, staggered memory access, and multicycling of computation units. Operation chaining involves chaining the primitive instructions, thereby eliminating unnecessary register file accesses and saving power. Pipelined execution of the vector instructions through the SIMD units improves the system throughput. Staggered execution of computation units helps simplify the data alignment networks. It is implemented in conjunction with multicycling so that the computation units are busy most of the time. The proposed architecture is evaluated with an in-house architecture emulator which uses component-level area and power models built with Synopsys and Artisan tools. Our results show that for WCDMA 2 Mbps, the proposed architecture uses two processors and consumes only 120 mW while SODA uses four processors and consumes 210 mW when implemented in 0.13-μm technology and clocked at 300 MHz.

High-speed and low-power electro-optical DSP coprocessor

A fast, power-efficient electro-optical vector-by-matrix multiplier (VMM) architecture is presented. Careful design of an electrical unit supporting high-speed data transfer enables this architecture to overcome bottlenecks encountered by previous VMM architectures. Based on the proposed architecture, we present an electro-optical digital signal processing (DSP) coprocessor that can achieve a significant speedup of 2-3 orders of magnitude over existing DSP technologies and execute more than 16 teraflops. We show that it is feasible to implement the system using off-the-shelf components, analyze the performance of the architecture with respect to primitive DSP operations, and detail the use of the new architecture for several DSP applications.