Low Power CMOS Image Sensor Research Articles

A Low-Voltage 0.7 µm Pixel with 6000 e- Full-Well Capacity for a Low-Power CMOS Image Sensor

A low-voltage pixel with 0.7 µm pitch was designed for a low-power CMOS image sensor. By reducing a pixel power supply voltage (Vpix), power consumption for pixel was reduced, but full-well capacity (FWC) was also decreased. However, by lowering the conversion gain (CG) and applying a negative voltage to the ground (NGND) of the pixel, FWC of 6000 e- was achieved without any degradation of both charge transfer lags and backflow noise. In addition, the signal linearity in the reduced analog-to-digital (ADC) range was improved by optimizing the source follower (SF). For dark performances, white spots and dark current worsened by NGND were significantly improved by forcing more negative voltage to the transfer gate (TG) when it was turned off.

Low Power CMOS Image Sensors Using Two Step Single Slope ADC With Bandwidth-Limited Comparators & Voltage Range Extended Ramp Generator for Battery-Limited Application

This paper proposes a low-power column-parallel two-step single slope Analog-to-Digital Converter (SS ADC) and voltage range tuned ramp generator for low-power CMOS Image Sensors (CIS). The proposed SS ADC has small bandwidth to drive the low power CMOS Image Sensors, without sacrificing the bandwidth performance. The ADC errors caused by the limited bandwidth can be resolved using dual CDS (Correlated Double Sampling) and using voltage range tuned ramp generator. The proposed two-step structure consists of a resistor DAC (coarse ramp) and a current DAC (fine ramp). The fine ramp has one slope generator, regardless of results of coarse ramp decisions, to remove the mismatch of slope between fine ramp slopes. This sensor of $960\times720$ pixels has been fabricated with 90 nm CMOS process. The measurement results demonstrate that proposed column parallel CDS circuits can achieve the current consumption is about $2~\mu \text{A}$ with 50 MHz main clock frequency, which is less than 33 % of other reports. The frame rate of the proposed CMOS Image Sensors (CIS) is maximum 35 fps. The proposed circuit has a redundancy error correction logic for to calibrate error between coarse and fine conversions. Total power consumption 28 mW from supply voltages of 2.8 V (analog) and 1.5 V (digital).

Low‐power column counter with a logical‐shift algorithm for CMOS image sensors

The authors propose a column counter that uses a logical-shift algorithm in column-parallel single-slope ADCs for low-power CMOS image sensors. The proposed column counter lowers power consumption by reducing the amount of internal toggling nodes and parasitic capacitance. Simulation results showed a 32% reduction in power consumption and a 60% reduction in the power-delay product compared to a conventional up/down counter.

CMOS Image Sensor for Lateral Flow Immunoassay Readers

Point-of-care (POC) systems for the detection of infectious diseases are in great demand especially in developing countries. Lateral flow immunoassays are considered ideal biosensors for POC diagnostics due to their numerous advantages. However, to quantify their results a low power, robust electronic reader is needed. A low power CMOS image sensor is presented that can be used in quantitative lateral flow immunoassay readers. It uses a single low power processing capacitive transimpedance amplifier architecture which includes noise cancellation. A chip containing $4\times 64$ pixels was fabricated in CMOS 0.35- $\mu\text{m}$ technology. With uniform illumination at 525 nm and 67 frames/s the chip has 1.9 mVrms total output referred noise and a total power consumption of 21 $\mu\text{W}$ . In tests with lateral flow immunoassays the chip detected concentrations of influenza A nucleoprotein from 0.5 ng/mL to 200 ng/mL.

A Low-power CMOS Image Sensor Based on Variable Frame Rate Operation

A Low-power CMOS Image Sensor Based on Variable Frame Rate Operation

A High-speed Low-power CMOS Image Sensor with Delta and Interpolation Readout Scheme

A High-speed Low-power CMOS Image Sensor with Delta and Interpolation Readout Scheme

A Low-Power CMOS Image Sensor With Area-Efficient 14-bit Two-Step SA ADCs Using Pseudomultiple Sampling Method

This brief presents a low-power CMOS image sensor with 14-bit column-parallel two-step (TS) successive approximation (SA) analog-to-digital converters (ADCs). The proposed TS SA ADC adopts a pseudomultiple sampling method to reduce the power consumption and the area. For implementing the 14-bit ADC, it only uses a capacitor digital-to-analog converter of 6 bits rather than 14 bits. The multiple sampling also suppresses the noise of a pixel and a column-parallel ADC. The image sensor is fabricated by using the 0.13-μm CMOS process. The measurement results show that the temporal noise is 82.7 μVrms, and the power consumption is 55.1 μW for one column ADC with a programmable gain amplifier. With the digital correlated double sampling and the TS calibration method, the proposed ADC achieves the column fixed-pattern noise of 0.98 LSB and a differential nonlinearity of +0.99/-0.90 LSB.

A 64 fJ/step 9-bit SAR ADC Array With Forward Error Correction and Mixed-Signal CDS for CMOS Image Sensors

A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490μm×7.4μm and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18 μm technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit.

A Low Power Image Sensor Controller and JPEG Encoder IC for Wireless Capsule Endoscopy

In this paper, a low power CMOS image sensor controller and baseline JPEG compression encoder for wireless capsule endoscopy is presented. The proposed JPEG encoder can be integrated into a wireless capsule system to compresses the raster YCbCr 4:2:2 raw image data from image sensor into JPEG format file and then send to external receiver through wireless transmission. To achieve low power and high image compression ratio, the JPEG compression algorithm is optimized for biomedical image compression. The compressed image data are being packed into byte format and DMA can be used to retrieve the JPEG image. The JPEG image compression chip is designed using 0.18-μm CMOS technology. It consumes 1.69 mW under 6 MHz system clock for VGA (640×480) image resolution when compressing at 7.5 frames per second.