Low-power Circuit Implementation Research Articles

A Real-Time-Link-Adaptive Operation Scheme for Maximum Energy Storage Efficiency in Resonant CM Wireless Power Receivers

The development, analysis, and experimental validation of an energy storage algorithmic scheme for performance optimization of resonant inductive power receivers are presented. Motivated by the crucial role of efficient energy storage in the next generation of brain-implantable devices, we introduce an energy management strategy in the design of wireless powering links, in which, the key performance measure is the energy stored during a limited time interval rather than the average energy delivered to the load. The presented strategy is proven analytically to yield the theoretically-maximum energy storage efficiency over a pre-determined period of time. Additionally, thanks to the algorithm's closed-form solution, the optimization can be done in real time, offering the potential for a solution that is adaptive to any variations in physical (e.g., coil separation, Rx rotation, etc.) and/or electrical (e.g., Q-factor, media conductivity, etc.) properties of the link, conditional to a low-power circuit implementation for its evaluation. The efficacy and precision of the solution obtained from the presented analytical model is confirmed with CAD-based simulation results, and later validated using experimental measurements. Our experimental results for two links with different characteristics (resonance frequency, coils size and separation, etc.) show a 52.5% and 67.5% improvement in overall energy storage efficiency compared to the standard CM receiver design in which resonance-to-charging switching is performed when the receiver's LC tank energy accumulation starts to saturate. This is while the presented method does not require any calibration and is designed to be employed by any generic current-mode receiver.

一种低面积低功耗RGB到YCbCr色彩空间转换电路实现方法

本文提出了一种低面积低功耗RGB与YCbCr色彩空间转换的电路实现方法。首先提出一种结合简化加法器图(Reduced Adder Graph, RAG)的公共子表达式消除(Common Subexpression Elimination, CSE)的电路实现，然后提出一个提高精度的补偿方法。最后采用TSMC 0.18um工艺对所提出的算法进行综合和布局布线。仿真和综合结果表明相比于传统的正则有符号数字(Canonic Signed Digit, CSD)编码系统，采用本文提出的结合CSE和RAG的RGB到YCbCr空间转换电路实现方法面积和功耗减小了20%，补偿算法提高了系统精度。 This paper presents a low-area and low-power circuit implementation of high-precision color space conversion from RGB to YCbCr. Firstly, an efficient circuit implementation combining com-mon-subexpression-elimination (CSE) with reduced-adder-graph (RAG) is presented. Secondly, a compensation method is proposed to enhance the precision. Finally, the synthesized results of a TSMC 0.18 um standard cell library are given. By using the proposed circuit implementation of color space conversion from RGB to YCbCr combining CSE and RAG without compensation, the results show that the area and power are reduced by about 20% than the traditional Canonic Signed Digital (CSD) method. With the compensation algorithm, the precision is much higher.

Design of a Low-Power On-Body ECG Classifier for Remote Cardiovascular Monitoring Systems

In this paper, we first present a detailed study on the trade-off between the computational complexity (directly related to the power consumption) and classification accuracy for a number of classifiers for classifying normal and abnormal electrocardiograms (ECGs). In our analysis, we consider the spectral energy of the constituent waves of the ECG as the discriminative feature. Starting with the exhaustive exploration of single heartbeat-based classification to ascertain the complexity-accuracy trade-off in different classification algorithms, we then extend our study for multiple heartbeat-based classification. We use data available in Physionet as well as samples from Southampton General Hospital Cardiology Department for our investigation. Our primary conclusion is that a classifier based on linear discriminant analysis (LDA) achieves comparable level of accuracy to the best performing support vector machine classifiers with advantage of significantly reduced computational complexity. Subsequently, we propose an ultra low-power circuit implementation of the LDA classifier that could be integrated with the ECG sensor node enabling on-body normal and abnormal ECG classification. The simulated circuit is synthesized at 130 nm technology and occupies 0.70 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> of silicon area (0.979 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> after place and route) while it consumes 182.94 nW @ 1.08 V, estimated with Synopsys PrimeTime when operating at 1 KHz. These results clearly demonstrate the potential for low-power implementation of the proposed design.

Numerical analysis of the new Implant-Free Quantum-Well CMOS: DualLogic approach

The research into alternative channel materials to improve CMOS performance is a rapidly growing area of research. III–V and Ge based MOSFETs offer attractive possibilities for a high performance and low power circuit implementation. Here, we report a global performance analysis of future DualLogic CMOS based on the new, Implant-Free Quantum-Well device architecture for both III–V nMOSFETs and Ge pMOSFETs. The III–V nMOSFETs are optimised to achieve low leakage, high performance and its performance is evaluated using ensemble Monte Carlo simulations. A similar approach is adopted for the Ge pMOSFETs. In addition, the impact of the interface states density on the output characteristics is also studied. Finally, the timing performance of the DualLogic CMOS is evaluated using mixed mode TCAD and circuit simulations.

Low-power circuit implementation for partial-product addition using pass-transistor logic

A low-power circuit implementation that performs partial-product addition within a 16/spl times/16-bit parallel multiplier is presented. The circuits are based on 0.8 /spl mu/m and 0.35 /spl mu/m BiCMOS processes and utilise mainly pass-transistor logic circuits. Unlike other pass-transistor implementations reported, the proposed circuits fully exploit the non-full-swing nature of the pass-transistor circuits, thus achieving low power operation. Despite the poorer current drive capability of the non-full-swing nodes, speed performance is maintained by stacking as few pass transistors in series as possible, and keeping the capacitive loading of the non-full-swing nodes as low as possible. The proposed implementation consists of a low-power 32-bit carry-select (CS) two-operand adder and a Wallace tree adder utilising a non-full-swing pass-transistor 4-2 compressor. Significant improvement in terms of power has been achieved when compared with existing circuits, thus making the proposed implementation suitable for a low-power high performance multipliers.