Low Power Budget Research Articles

ShaderNN: A lightweight and efficient inference engine for real-time applications on mobile GPUs

Inference using deep neural networks on mobile devices has been an active area of research in recent years. The design of a deep learning inference framework targeted for mobile devices needs to consider various factors, such as the limited computational capacity of the devices, low power budget, varied memory access methods, and I/O bus bandwidth governed by the underlying processor’s architecture. Furthermore, integrating an inference framework with time-sensitive applications — such as games and video-based software to perform tasks like ray tracing denoising and video processing — introduces the need to minimize data movement between processors and increase data locality in the target processor. In this paper, we propose Shader Neural Network (ShaderNN), an OpenGL-based, fast, and power-efficient inference framework designed for mobile devices to address these challenges. Our contributions include the following: (1) the texture-based input/output provides an efficient, zero-copy integration with real-time graphics pipelines or image processing applications, thereby saving expensive data transfers between CPU and GPU, which are unavoidable in most existing inference engines; (2) we are the first to leverage fragment shaders based on the OpenGL backend in neural network inference operators, which has an advantage in deploying parametrically small neural network models; (3) a hybrid implementation of the compute shader and fragment shader is proposed that enables layer-level shader selection to boost performance; and (4) we utilize OpenGL features — such as normalization, interpolation and texture padding — to improve performance. Experiments illustrate the favorable performance of ShaderNN over other popular on-device deep learning frameworks such as TensorFlow-Lite on the latest mobile devices powered by Qualcomm and MediaTek chips. A case study further demonstrates the usability and integration of the ShaderNN framework with a media processing Android application seamlessly. ShaderNN is available open source at Github (https://github.com/inferenceengine/shadernn).

Maximisation of synchronisability under low injection power

Synchronisability of limit cycle oscillators has been measured by the width of the synchronous frequency band, known as the Arnold tongue, concerning external forcing. We clarify a fundamental limit on maximizing this synchronisability within a specified extra low power budget, which underlies an important and ubiquitous problem in nonlinear science related to an efficient synchronisation of weakly forced nonlinear oscillators. In this letter, injection-locked Class-E oscillators are considered as a practical case study, and we systematically analyse their power consumption; our observations demonstrate the independence of power consumption in the oscillator from power consumption in the injection circuit and verify the dependency of power consumption in the oscillator solely on its oscillation frequency. These systematic observations, followed by the mathematical optimisation establish the existence of a fundamental limit on synchronisability, validated through systematic circuit simulations. The results offer insights into the energetics of synchronisation for a specific class of injection-locked oscillators.

A temporal densely connected recurrent network for event-based human pose estimation

Event camera is an emerging bio-inspired vision sensors that report per-pixel brightness changes asynchronously. It holds noticeable advantage of high dynamic range, high speed response, and low power budget that enable it to best capture local motions in uncontrolled environments. This motivates us to unlock the potential of event cameras for human pose estimation, as the human pose estimation with event cameras is rarely explored. Due to the novel paradigm shift from conventional frame-based cameras, however, event signals in a time interval contain very limited information, as event cameras can only capture the moving body parts and ignores those static body parts, resulting in some parts to be incomplete or even disappeared in the time interval. This paper proposes a novel densely connected recurrent architecture to address the problem of incomplete information. By this recurrent architecture, we can explicitly model not only the sequential but also non-sequential geometric consistency across time steps to accumulate information from previous frames to recover the entire human bodies, achieving a stable and accurate human pose estimation from event data. Moreover, to better evaluate our model, we collect a large-scale multimodal event-based dataset that comes with human pose annotations, which is by far the most challenging one to the best of our knowledge. The experimental results on two public datasets and our own dataset demonstrate the effectiveness and strength of our approach. Code is available online for facilitating the future research.

Enhancing the Sustainability of Acoustic Backscatter Communication with Multi-Source Energy Harvesting

Backscatter Communication (BackCom) has opened up various novel joint sensing and communication applications in the Internet of things (IoT) domain. In particular, the IoT devices in water bodies have seen a recent paradigm shift toward more sustainability with the advent of Acoustic Backscatter Communication (A-BackCom). However, despite the low-power budget of A-BackCom, it only relies on harvesting energy from the source (acoustic) signal. In this paper, we survey some Multi- Source Energy Harvesting (MSEH) techniques from terrestrial BackCom which can be adopted to enhance the sustainability of ABackCom. We also show and discuss a case study where multiple energy sources are harvested in the water body and how much the harvested energy could extend the operation ABackCom. Further, we discuss some challenges of MSEH in ABackCom. Results from our case study show that MSEH in ABackCom could extend the lifetime of an A-BackCom node by allowing a recharging time as low as 5.7 ms, even without an acoustic carrier signal.

A Lightweight Mitigation Technique for Resource- Constrained Devices Executing DNN Inference Models Under Neutron Radiation

Deep neural network (DNN) models are being deployed in safety-critical embedded devices for object identification, recognition, and even trajectory prediction. Optimised versions of such models, in particular the convolutional ones, are becoming increasingly common in resource-constrained edge-computing devices (e.g., sensors, drones), which typically rely on reduced memory footprint, low power budget and low-performance microprocessors. DNN models are prone to radiation-induced soft errors, and tackling their occurrence in resource-constrained devices is a mandatory and substantial challenge. While traditional replication-based soft error mitigation techniques will likely account for a reasonable performance penalty, hardware solutions are even more costly. To undertake this almost contradictory challenge, this work evaluates the efficiency of a lightweight software-based mitigation technique, called Register Allocation Technique (RAT), when applied to a convolutional neural network (CNN) model running on two commercial Arm microprocessors (i.e., Cortex-M4 and M7) under the effects of neutron radiation. Gathered results obtained from two neutron radiation campaigns suggest that RAT can reduce the number of critical faults in the CNN model running on both Arm Cortex-M microprocessors. Results also suggest that the SDC FIT rate of the RAT-hardened CNN model can be reduced in up to 83% with a runtime overhead of 32%.

Fast Energy-Harvesting TEG-Supplied Charging Regulator Microsystem

This paper presents a fast hysteretic switched-inductor charging regulator (SLCR) microsystem. It is powered by on-chip thermoelectric generators (TEGs) to supply Internet-of-Things (IoT) wireless microsensors. On-chip TEGs are appealing because they are 12–1400× smaller than off-chip ones. IoT sensors mostly idle in low-power mode and transmit data wirelessly only in high-power mode on demand. This requires CMOS SLCRs to respond quickly to abrupt load dumps caused by IoT sensors. State-of-the-art (SoA) SLCRs respond to load dumps in 100 μs–2.5 ms. This time duration amounts to a significant portion of the IoT sensor's data transmission time (500 μs–7 ms). This slow response time jeopardizes the quality of data transmission. This paper presents a fast hysteretic control that responds in 9.6 μs. This control adopts nested hysteretic architecture and requires only three comparators and simple combinational logics, which is appealing, considering the low power budget limited by on-chip TEGs. Moreover, this paper contributes detailed stability analysis, derives response time and accuracy and provides intuitive and accurate system design equations. Measured results of a 180-nm CMOS prototype validate that the proposed system shortens response time by 10–260× compared to the SoA.

Active Reconfigurable Intelligent Surface-Assisted MISO Integrated Sensing and Communication Systems for Secure Operation

Spectrum congestion has motivated the recent introduction of integrated sensing and communication (ISAC) systems where radar and communications functionalities co-exist and share the same spectrum. This is accompanied by extensive research in the area of reconfigurable intelligent surfaces (RIS), thanks to their ability to improve the ISAC systems. In this paper, the physical layer security of a multiuser multiple-input single-output (MU-MISO) ISAC system is investigated when the system is subject to eavesdropping by a malicious unmanned aerial vehicle (UAV). In particular, we propose using an active RIS to maximize the achievable secrecy rate of the system through jointly designing the radar receive beamformers, the active RIS reflection coefficients matrix and the transmit beamformers at the dual-function base station of the ISAC system. This is done while taking into account a minimum radar detection signal-to-noise ratio (SNR) and total system power budget constraints. The resulting non-convex optimization problem is tackled by exploiting fractional programming (FP) and majorization-minimization (MM) techniques to achieve a solution. Our numerical results show the superiority of active RIS to achieve the goal when compared with passive RIS or with an ISAC without an RIS. Results also show that passive RIS could still be a viable solution to achieve this goal but at the expense of a much larger needed size especially when lower power budgets are available.

IRIS: A low duty cycle cross-layer protocol for long-range wireless sensor networks with low power budget

This paper presents a lightweight cross-layer protocol relIable Routing with coordInated medium acceSs control (IRIS) which is designed for long-range pipeline Wireless Sensor Networks (WSNs) with extremely low power budget, typically seen in a range of monitoring applications. IRIS includes functions of network discovery, medium access control and routing designed for heavily energy constrained networks. The protocol is able to operate with less than 1% duty cycle, thereby conforming to ISM band spectrum regulations in the 868MHz band. The duty cycle can be flexibly configured to meet other regulations/power budgets as well as to improve the route forming performance. Simulation results show a guaranteed route formation in different network topologies with various protocol configurations. An analytical model is presented to validate the simulation results of route formation time. System robustness against unreliable wireless connections and node failures are also demonstrated by simulations. A network of 71 attenuated LoRa nodes is implemented to evaluate the capability of IRIS. Long-term operation of the network shows consistent performance compare with the simulations.

Assessment of Winograd-based processor element for CNN processor and ASIC implementation of convolution processor element

The convolutional neural network (CNN) is the most widely used machine learning technique within the fields of image and video processing. It is primarily used to categorize images using vast datasets. This require a lot of calculations. The effectiveness of a field-programmable gate array (FPGA) as a hardware accelerator for CNNs will give excellent performance at low power budgets. The employment of the Winograd algorithm can reduce the number of processing stages in CNN. 2-D convolution is employed for the bulk of calculations in CNNs. The tactic for computing convolution for smaller filter sizes that uses Winograd minimum filtering is the handiest. The comparison of computation complexity for multiplications will be performed using Matlab. The architecture of the Winograd-based processing element, RTL coding in Verilog HDL, and the test bench are designed to examine the performance. The Xilinx Vivado / Cadence tool will be used to implement the processing element in the convolution unit on an FPGA or ASIC.

CS-Audio: A 16 pJ/b 0.1–15 Mbps Compressive Sensing IC With DWT Sparsifier for Audio-AR

With the expansion of sensor nodes to newer avenues of technologies, such as the Internet of things (IoT), internet of bodies (IoB), augmented reality (AR), and mixed reality, the demand to support high-speed operations, such as audio and video, with a minimal increase in power consumption is gaining much traction. In this work, we focus on these nodes operating in audio-based AR (AAR) and explore the opportunity of supporting audio at a low power budget. For sensor nodes, communicating one bit of data usually consumes significantly higher power than the power associated with sensing and processing/computing one data bit. Compressing the number of communication bits at the expense of a few computation cycles considerably reduces the overall power consumption of the nodes. Audio codecs such as AAC and LDAC that currently perform compression and decompression of audio streams burn significant power and create a floor to the minimum power possible in these applications. Compressive sensing (CS), a powerful mathematical tool for compression, is often used in physiological signal sensing, such as EEG and ECG, and it can offer a promising low-power alternative to audio codecs. We introduce a new paradigm of using the CS-based approach to realize audio compression that can function as a new independent technique or augment the existing codecs for a higher level of compression. This work, CS-Audio, fabricated in TSMC 65-nm CMOS technology, presents the first CS-based compression, equipped with an ON-chip DWT sparsifier for non-sparse audio signals. The CS design, realized in a pipelined architecture, achieves high data rates and enables a wake-up implementation to bypass computation for insignificant input samples, reducing the power consumption of the hardware. The measurement results demonstrate a 3X–15X reduction in transmitted audio data without a perceivable degradation of audio quality, as indicated by the perceptual evaluation of audio quality mean opinion score (PEAQ MOS) <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${&gt;}1.5$ </tex-math></inline-formula> . The hardware consumes 238 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$~\mu \text{W}$ </tex-math></inline-formula> power at 0.65 V and 15 Mbps, which is ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sim $ </tex-math></inline-formula> 20X–40X) lower than audio codecs.

Multi Gigabit Wireless Data Transfer in Detectors at Future Colliders

The WADAPT (Wireless Allowing Data And Power Transmission) consortium has been formed to identify the specific needs of different projects that might benefit from wireless communication technologies with the objective of providing a common platform for research and development in order to optimize effectiveness and cost. Wireless technologies have developed extremely fast over the last decade and are now mature enough to be a promising alternative to cables and optical links, with a possibility of revolutionizing detector design. Although wireless readout has the qualities and properties to be used in many collider detectors, this article focuses on the transmission of large amount of data from vertex detectors at high rate, low power budget and in potential high radiation environment. For vertex detectors, the 60 GHz band has proven to be adequate and commercial products are already available, providing 6 Gbps data links. This technology allows efficient partitioning of detectors in topological regions of interest, with the possibility of adding intelligence on the detector to perform four-dimensional reconstruction of the tracks and vertices online, in order to attach the tracks to their vertex with great efficiency even in difficult experimental conditions, and conveniently substitutes a mass of materials (cables and connectors). Early transceiver module products have been successfully tested for signal confinement, crosstalk, electromagnetic immunity and resistance to radiation. In the long run, emerging 140 GHz bands could also be used for higher data rates (&amp;gt;100 Gbps) at future high energy and luminosity hadron colliders.

Neuromorphic Time-Multiplexed Reservoir Computing With On-the-Fly Weight Generation for Edge Devices.

The human brain has evolved to perform complex and computationally expensive cognitive tasks, such as audio-visual perception and object detection, with ease. For instance, the brain can recognize speech in different dialects and perform other cognitive tasks, such as attention, memory, and motor control, with just 20 W of power consumption. Taking inspiration from neural systems, we propose a low-power neuromorphic hardware architecture to perform classification on temporal data at the edge. The proposed architecture uses a neuromorphic cochlea model for feature extraction and reservoir computing (RC) framework as a classifier. In the proposed hardware architecture, the RC framework is modified for on-the-fly generation of reservoir connectivity, along with binary feedforward and reservoir weights. Also, a large reservoir is split into multiple small reservoirs for efficient use of hardware resources. These modifications reduce the computational and memory resources required, thereby resulting in a lower power budget. The proposed classifier is validated for speech and human activity recognition (HAR) tasks. We have prototyped our hardware architecture using Intel's cyclone-10 low-power series field-programmable gate array (FPGA), consuming only 4790 logic elements (LEs) and 34.9-kB memory, making it a perfect candidate for edge computing applications. Moreover, we have implemented a complete system for speech recognition with the feature extraction block (cochlea model) and the proposed classifier, utilizing 15 532 LEs and 38.4-kB memory. By using the proposed idea of multiple small reservoirs along with on-the-fly generation of reservoir binary weights, our architecture can reduce the power consumption and memory requirement by order of magnitude compared to existing FPGA models for speech recognition tasks with similar complexity.

Energy-Efficient Precision-Scaled CNN Implementation With Dynamic Partial Reconfiguration

A convolutional neural network (CNN) classifies images with high accuracy. However, CNN operation requires a large number of computations which consume a significant amount of power when implemented on hardware. Precision scaling has been recently used to reduce the hardware requirements and power consumption. In this paper, we present an energy-efficient precision-scaled CNN (EEPS-CNN) architecture. Furthermore, the Field Programmable Gate Array (FPGA) is reconfigured during run time using Dynamic Partial Reconfiguration (DPR). If the battery level decreases, the EEPS-CNN design with the most appropriate power consumption is configured on the FPGA. DPR enables recognition applications to run at a low power budget while sacrificing minor accuracy instead of termination. The proposed architecture is implemented on Xilinx XC7Z020 FPGA and is evaluated on three datasets: MNIST, F-MNIST, and SVHN datasets. The results show a 2.2X, 2.39X, and 2.38X reduction in the energy consumption, respectively, while using only 7 bits to represent all inputs and network parameters. The accuracy of the proposed EEPS-CNN is only 0.53%, 3.67%, and 0.88% less than 32-bit floating-point architectures for MNIST, F-MNIST, and SVHN, respectively. Moreover, the results show up to 92.91X and 4.84X reductions in the power and energy consumption of the proposed EEPS-CNN compared to related designs developed for the MNIST dataset.

Iris: A Low Duty Cycle Cross-Layer Protocol for Long-Range Wireless Sensor Networks with Low Power Budget

This paper presents a cross-layer protocol (IRIS) designed for long-range pipeline Wireless Sensor Networks with extremely low power budget, typically seen in a range of monitoring applications. IRIS uses ping packets initiated by a base station to travel through the multi-hop network and carry monitoring information. The protocol is able to operate with less than 1% duty cycle, thereby conforming to ISM band spectrum regulations in the 868MHz band. The duty cycle can be flexibly configured to meet other regulations/power budgets as well as to improve the route forming performance. Simulation results show guaranteed route formation in different network topologies with various protocol configurations. System robustness against unreliable wireless connections and node failures are also demonstrated by simulations.

Efficient photoconductive terahertz detection through photon trapping in plasmonic nanocavities

We present a photoconductive terahertz detector that employs a plasmonic nanocavity to offer high-sensitivity and broadband operation when used in a terahertz time-domain spectroscopy system even at very low optical pump power levels. By employing a plasmonic nanocavity, all of the photocarriers are generated within a 100 nm distance from the photoconductor contact electrodes, enabling a short transport time for almost all of the photogenerated carriers. As a result, the photoconductive detector maintains high quantum efficiency and ultrafast operation simultaneously, enabling high-sensitivity and broadband operation at very low optical pump power levels. We utilize a photoconductive detector based on a plasmonic nanocavity optimized for operation at a 770 nm optical wavelength in a terahertz time-domain spectroscopy system and demonstrate a 100 dB signal-to-noise ratio and a 0.1–6 THz noise-equivalent bandwidth at a record-low average optical pump power of 0.1 mW, compared to the state-of-the-art photoconductive terahertz detectors. The extremely low optical power budget of the demonstrated photoconductive detector makes this detector attractive for multi-pixel terahertz imaging systems.

Prospect of Spintronics in Neuromorphic Computing

AbstractNeuromorphic computing emulates a biological brain at different levels of the computer hierarchy by exploiting brain‐inspired principles in designing novel devices, algorithms, and architectures. It is believed to have a lower power budget and a higher efficiency in performing cognitive tasks, and is arguably the most promising approaches for next‐generation artificial intelligence. Despite the potentials, progress of neuromorphic computing is constrained by a lack of dedicated hardware. Spintronics is a fast‐evolving discipline that exploits the spin degree of freedom in electronics. The interplay of magnetic and electrical properties of spintronic devices gives rise to a wide range of amazing phenomena, which are both intrinsically conducive to neuromorphic computing and highly compatible with conventional manufacturing technologies. Here, the development of neuromorphic computing with reference to spintronics is reviewed. The state‐of‐the‐art spintronic technologies, such as the magnetic tunnel junction, spin–orbit torque, domain wall propagation, magnetic skyrmions, and antiferromagnet, are highlighted and how they can used for artificial neurons and synapses in different artificial neural networks are discussed. The technical challenges to be overcome for realizing more powerful all‐spin artificial neural networks are also evaluated.

Low Power Clock Generator Design With CMOS Signaling

The requirements for computing with higher energy efficiency in the datacenter and for longer battery life in laptop computers, cell phones, and other IoT devices while increasing performance with higher frequency and more cores, drive the needs for more clock generators with increased performance (frequency and jitter) and lower power budgets. The traditional current mode low swing clock generators were used widely in industry about 10 years ago. Although it had the advantage of higher supply noise rejection due to the differential nature of the architectures, however, it had the disadvantages of high-power consumption, large layout area, and not friendly to process scaling. Contrary to current mode low swing design, clock generator architectures with CMOS large swing signaling, which have advantages of low power consumption, small area, and based on circuits friendly to process scaling, have been widely adopted for clocking generation in the industry since 2009. In this paper, phase locked loops, delay locked loops, phase interpolators, high resolution digital to time converter and clock distribution techniques with CMOS large swing signaling will be discussed and reviewed.

Test results of ATLASPIX3 — A reticle size HVCMOS pixel sensor designed for construction of multi chip modules

High voltage CMOS pixel sensors will be or are proposed to be used in several particle physics experiments for particle tracking like Mu3e experiment. ATLASPIX3 is the first full reticle size monolithic HVCMOS sensor for construction of multi-chip modules. The specifications for the use case have been taken from ATLAS pixel upgrade in fifth layer where it was a candidate for. The size of the chip is 2.0×2.1 cm2 with periphery at one side which makes the chip 3-side buttable. ATLASPIX3 has been implemented in a standard 180 nm HVCMOS process. Each pixel has an area of 150×50μm2 and contains a large charge collecting electrode implemented as deep n-well. The depleted volume around the n-well is enlarged by a high voltage bias and the usage of higher resistivity substrate. The readout electronics supports both triggered and triggerless readout with zero-suppression. ATLASPIX3 could be used for the construction of CMOS modules for particle tracking in experiments where high time resolution, high radiation tolerance, low power and low material budget are required. In the design phase, special attention has been paid to decreasing timing differences between pixels and the rate capability of the readout.

A wide tuning range, low noise oscillator with FoM of -188 dBc/Hz in 45 nm CMOS

A wide tuning range, low phase noise oscillator with 3 stage differential configuration is presented. GPDK 45 nm CMOS Technology is selected for the design and simulation of the proposed circuit, under power supply impediment of 1.1 V. Proposed delay cell features ultra wide tuning range as it utilizes dual control voltages (Vc1 and Vc2), enabling large current to flow in the circuit. As frequency of oscillation has linear proportionality with the bias current, this oscillator generates frequencies from 534 MHz to 18.56 GHz. The proposed circuit occupies chip area of 102.87μm2. This circuit offers power consumption of 1.13 mWatt and phase noise of −108.61 dBc/Hz (10 MHz offset frequency) at 5.82 GHz oscillation frequency. Performance of the proposed circuit is evaluated on various temperature, supply voltage and process corners. Total Harmonic Distortion (THD) profile is also measured through simulation. Because of wide frequency spectrum, low phase noise, small area and low power budget, proposed circuit can be utilized in various power electronic applications, medical equipments, communication and navigation systems.

DTN and Non-DTN Routing Protocols for Inter-CubeSat Communications: A comprehensive survey

CubeSats, which are limited by size and mass, have limited functionality. These miniaturised satellites suffer from a low power budget, short radio range, low transmission speeds, and limited data storage capacity. Regardless of these limitations, CubeSats have been deployed to carry out many research missions, such as gravity mapping and the tracking of forest fires. One method of increasing their functionality and reducing their limitations is to form CubeSat networks, or swarms, where many CubeSats work together to carry out a mission. Nevertheless, the network might have intermittent connectivity and, accordingly, data communication becomes challenging in such a disjointed network where there is no contemporaneous path between source and destination due to satellites’ mobility pattern and given the limitations of range. In this survey, various inter-satellite routing protocols that are Delay Tolerant (DTN) and Non Delay Tolerant (Non-DTN) are considered. DTN routing protocols are considered for the scenarios where the network is disjointed with no contemporaneous path between a source and a destination. We qualitatively compare all of the above routing protocols to highlight the positive and negative points under different network constraints. We conclude that the performance of routing protocols used in aerospace communications is highly dependent on the evolving topology of the network over time. Additionally, the Non-DTN routing protocols will work efficiently if the network is dense enough to establish reliable links between CubeSats. Emphasis is also given to network capacity in terms of how buffer, energy, bandwidth, and contact duration influence the performance of DTN routing protocols, where, for example, flooding-based DTN protocols can provide superior performance in terms of maximizing delivery ratio and minimizing a delivery delay. However, such protocols are not suitable for CubeSat networks, as they harvest the limited resources of these tiny satellites and they are contrasted with forwarding-based DTN routing protocols, which are resource-friendly and produce minimum overheads on the cost of degraded delivery probability. From the literature, we found that quota-based DTN routing protocols can provide the necessary balance between delivery delay and overhead costs in many CubeSat missions.