Low-power Automatic Gain Control Research Articles

A 6 μW per channel analog biomimetic cochlear implant processor filterbank architecture with across channels AGC.

A new analog cochlear implant processor filterbank architecture of increased biofidelity, enhanced across-channel contrast and very low power consumption has been designed and prototyped. Each channel implements a biomimetic, asymmetric bandpass-like One-Zero-Gammatone-Filter (OZGF) transfer function, using class-AB log-domain techniques. Each channel's quality factor and suppression are controlled by means of a new low power Automatic Gain Control (AGC) scheme which is coupled across the neighboring channels and emulates lateral inhibition (LI) phenomena in the auditory system. Detailed measurements from a five-channel silicon IC prototype fabricated in a 0.35 μm AMS technology confirm the operation of the coupled AGC scheme and its ability to enhance contrast among channel outputs. The prototype is characterized by an input dynamic range of 92 dB while consuming only 28 μW of power in total ( ∼ 6 μW per channel) under a 1.8 V power supply. The architecture is well-suited for fully-implantable cochlear implants.

A low power automatic gain control loop for a receiver

This paper proposes a new structure to lower the power consumption of a variable gain amplifier (VGA) and keep the linearity of the VGA unchanged. The structure is used in a high rate amplitude-shift keying (ASK) based IF-stage. It includes an automatic gain control (AGC) loop and ASK demodulator. The AGC mainly consists of six-stage VGAs. The IF-stage is realized in 0.18 μm CMOS technology. The measurement results show that the power consumption of the whole system is very low. The system consumes 730 μA while operating at 1.8 V. The minimum ASK signal the system could detect is 0.7 mV (peak to peak amplitude).

A 0.9 V 96 $\mu$W Fully Operational Digital Hearing Aid Chip

A 0.9 V 96 muW fully operational low-power digital hearing aid chip is proposed and implemented. An internal status controller is introduced to achieve full operation of the adaptive-SNR analog front end. Dedicated DSP with an additional volume control parameter eliminates any internal overflow and enables the hearing aid to be customized for each individual user. When the input audio band is split into a low band and a high band, the audio signal can be processed coarsely. In addition, fine processing of the high-band signal can be obtained with a low-power automatic gain control (AGC) comprising a digital comparator and a subtraction unit. A heterogeneous Sigma-Delta DAC reduces the power consumption of the interpolation filter without degrading performance by allowing different frequencies between the input signal and the sampling clock of the Sigma-Delta modulator. Compared with a conventional Sigma-Delta DAC, the heterogeneous Sigma-Delta DAC reduces the power dissipation by 40.4% and the area occupation by 40.5%, and it has a reported error rate of only 0.16%. The fabricated chip achieves a 79 dB peak SNR with 4.1 muVrms of input-referred noise voltage. The core area is 2.8 mm x 1.1 mm in a 0.18 mum standard CMOS process.