Low-power Analog Circuit Design Research Articles

Surface-Potential-Based Analytical Model of Low-Frequency Noise for Planar-Type Tunnel Field-Effect Transistors

Analytical models of low-frequency noise (LFN) characteristics for planar-type tunnel field-effect-transistors (TFETs) are proposed. A surface-potential-based current-voltage model is developed to physically represent the current fluctuation due to charge trapping/detrapping in the gate dielectric. An LFN model can be analytically derived from the current fluctuation with a reasonable approximation. The proposed model is verified using Technology Computer Aided Design (TCAD) and measurement data, which are in good agreement with each other. The analytical model can not only serve as a valuable reference and tool for low-power analog circuit design but also provide physical insights into the LFN of TFETs.

Non-GCA modeling of near threshold I-V characteristics of DG MOSFETs

This work focuses on modeling of near threshold region (Vgs − Vt < a few kT/q) of DG (Double-Gate) MOSFETs with velocity saturation. Accurate modeling of this region is important for design of low-power analog circuits. A non-GCA (Gradual Channel Approximation) model is developed that takes the nonlinear dependence of inversion charge density on quasi-Fermi potential near threshold into account. It has been applied to both n = 1 and n = 2 velocity saturation models. The I-V characteristics generated by the model are consistent with TCAD simulations.

Nanoscale MOSFET Modeling: Part 1: The Simplified EKV Model for the Design of Low-Power Analog Circuits

This article presents the s implified charge-based Enz-Krummenacher-Vittoz (EKV) [11] metal-oxide-semiconductor field-effect transistor (MOSFET) model and shows that it can be used for advanced complementary metal-oxide-semiconductor (CMOS) processes despite its very few parameters. The concept of an inversion coefficient (IC) is first introduced as an essential design parameter that replaces the overdrive voltage VG-VT0 and spans the entire range of operating points from weak via moderate to strong inversion (SI), including the effect of velocity saturation (VS). The simplified model in saturation is then presented and validated for different 40- and 28-nm bulk CMOS processes. A very simple expression of the normalized transconductance in saturation, valid from weak to SI and requiring only the VS parameter mc, is described. The normalized transconductance efficiency Gm/ID, which is a key figure-of-merit (FoM) for the design of low-power analog circuits, is then derived as a function of IC including the effect of VS. It is then successfully validated from weak to SI with data measured on a 40-nm and two 28-nm bulk CMOS processes. It is then shown that the normalized output conductance Gds/ID follows a similar dependence with IC than the normalized Gm/ID characteristic but with different parameters accounting for drain induced barrier lowering (DIBL). The methodology for extracting the few parameters from the measured ID-VG and ID-VD characteristics is then detailed. Finally, it is shown that the simplified EKV model can also be used for a fully depleted silicon on insulator (FDSOI) and Fin-FET 28-nm processes.

Bulk-driven floating-gate and bulk-driven quasi-floating-gate techniques for low-voltage low-power analog circuits design

In this paper, novel non-conventional techniques,11Note: In this paper the presented techniques are a national patent application registered by the Industrial Property Office in the Czech Republic under registration number 303698, for year 2013 [56]. named by the author of this paper “bulk-driven floating-gate (BD-FG)” MOS transistor (MOST) and “bulk-driven quasi-floating-gate (BD-QFG) MOST” for low-voltage (LV) low-power (LP) analog circuit design are presented. These novel techniques appear as a good solution to merge the advantages of floating-gate (FG) and quasi-floating-gate (QFG) with the advantages of bulk-driven (BD) technique and suppress their disadvantages. Consequently, the transconductance and transient frequency of BD-FG and BD-QFG MOSTs approach the conventional gate driven (GD) MOST values. Furthermore, a novel LV LP class AB second generation current conveyor based on BD-FG MOST is presented in this paper as an example. The supply voltage is only ±0.4V with a rail-to-rail voltage swing capability and total power consumption of mere 10μW. PSpice simulation results using the 0.18μm P-well CMOS technology are included to confirm the attractive properties of these new techniques.

Design methodology for ultra low-power analog circuits using next generation BSIM6 MOSFET compact model

The recently proposed BSIM6 bulk MOSFET compact model is set to replace the hitherto widely used BSIM3 and BSIM4 models as the de-facto industrial standard. Unlike its predecessors which were threshold voltage based, the BSIM6 core is charge based and thus physically continuous at all levels of inversion from linear operation to saturation. Hence, it lends itself conveniently for the use of a design methodology suited for low-power analog circuit design based on the inversion coefficient (IC) that has been extensively used in conjugation with the EKV model and allows to make simple calculations of, for example, transconductance efficiency, gain bandwidth product, etc. This methodology helps to make a near-optimal selection of transistor dimensions and operating points even in moderate and weak inversion regions. This paper will discuss the IC based design methodology and its application to the next generation BSIM6 compact MOSFET model.