Low-power 8-bit Research Articles

A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices

Rapid advancements in micro-machining and microelectronics over the last few years have accelerated the growth of implanted medical devices that greatly improve a person's life. These devices first gather the signals from different nodes in/on the body, and then, they condition, multiplex, and digitize the signals. Thus, an analog-to-digital converter (ADC), which must continuously convert a variety of analog electrophysiological signals to digital codes, is one of the most crucial and power-hungry components. For implantable medical devices, the successive approximation register (SAR) ADC is a good choice. In this paper, a low-power single-ended SAR ADC architecture is proposed to offer good compromises between power efficiency, conversion accuracy, and design complexity. The proposed architecture supports 8-bit resolution at a sampling rate of 1 MS/s. Using a 130-nm CMOS process with 1.2 V supply voltage, an effective number of bits (ENOB) of 7.3 dB is achieved while 28.5 μW power is consumed. The ADC core only occupies an active area of about 197 μm × 377 μm.

A low power 16-bit 50 MS/s pipeline ADC with 104 dB SFDR in 0.18 μm CMOS

This paper presents a low-power 16-bit 50-MS/s pipeline analog-to-digital converter (ADC). An improved switched-capacitor bias technique is proposed to reduce power consumption while maintaining excellent performance, and a novel bootstrapped switch is implemented to improve the linearity further. An INL-(integral nonlinearity) based capacitor mismatch calibration is proposed to calibrate the capacitor match accuracy to the 16-bit level. The pipeline ADC is fabricated in a 0.18 μm mixed-signal CMOS process and the core size is 1.8 mm2. The implemented ADC is measured at a 50 MHz sampling rate under 1.8 V supply. After foreground calibration for capacitor mismatch errors, it achieves beyond 100 dB spur-free dynamic range (SFDR) and 75.3 dB signal-to-noise ratio (SNR). At the same time, the power consumption is 70.2 mW with 0.29 pJ/conv-step FOM (Figures-of-Merit).

Design of 4-bit absolute value detector with low energy

The article highlights the latest developments in the design of low-power 4-bit Absolute Value Detector (AVD) circuits that are utilized in digital signal processing (DSP) applications. DSP applications like audio and video processing, biological signal processing, and digital communication systems rely heavily on the AVD circuit, which determines the absolute value of an input signal. The article introduces a low-energy 4-bit AVD circuit based on pass transistors that incorporates advanced optimization techniques like adiabatic logic, approximation techniques, and layout optimization. This optimized AVD circuit achieves remarkable results in terms of power consumption and energy efficiency. With a power consumption of just 0.6 nW and an energy efficiency of 0.6 pJ per cycle, the circuit maintains precision and rapid response time. These advancements in AVD circuit design can be highly beneficial for portable and battery-powered devices such as earplugs, implants, and cell phones, as well as electronic components like Static Random Access Memory (SRAM) and motherboards. Overall, the proposed low-energy 4-bit AVD circuit is a significant development in the DSP field, enabling more efficient and effective processing of digital signals.

An optimization of low power 4-bit PAL FIR filter using adiabatic techniques

An optimization of low power 4-bit PAL FIR filter using adiabatic techniques

The design of a low-power 4-bit barrel shifter for a current steering DAC using optimized multiplexers in 65 nm technology

CMOS technology scaling has paved the way for a faster and more complex integration. Low-power techniques have become crucial because of the demand for low power consumption and high speed. The main objective of this research is to utilize low-power techniques to implement a 4-bit barrel shifter that can shift or rotate data using any number of bits within a single cycle. Gate Diffusion Input (GDI), modified GDI, and full-swing GDI logic have been employed to implement a 2:1 multiplexer, among which the modified GDI-based multiplexer stands out because of its minimal power consumption. Consequently, a 4-bit barrel shifter is implemented using a modified GDI-based multiplier. All designs and simulations were performed using the Cadence Virtuoso tool in UMC 65 nm technology. This technology enables the accurate analysis and assessment of the designed barrel shifter, considering the characteristics and limitations of the 65 nm process. This study focused on leveraging low-power techniques to implement a 4-bit barrel shifter to address the industry's demand for power-efficient solutions. The modified GDI-based multiplexer is a promising choice that provides a balance between low power consumption and high performance. The use of advanced design tools and selected technology further ensures accurate simulations and evaluations of the proposed design.

Design of a Low-Power and Low-Area 8-Bit Flash ADC Using a Double-Tail Comparator on 180 nm CMOS Process

This paper presents a low-area 8-bit flash ADC that consumes low power. The flash ADC includes four main blocks-an analog multiplexer (MUX), a comparator, an encoder, and an SPI (Serial Peripheral Interface) block. The MUX allows the selection between eight analog inputs. The comparator block contains a TIQ (Threshold Inverter Quantization) comparator, a control circuit, and a proposed architecture of a Double-Tail (DT) comparator. The advantage of using the DT comparator is to reduce the number of comparators by half, which helps reduce the design area. The SPI block can provide a simple way for the ADC to interface with microcontrollers. This mixed-signal circuitry is designed and simulated using 180 nm CMOS technology. The 8-bit flash ADC only employs 128 comparators. The applied input clock is 80 MHz, with the input voltage ranging from 0.6 V to 1.8 V. The comparator block outputs 127 bits of thermometer code and sends them to the encoder, which exports the seven least significant bits (LSB) of the binary code. The most significant bit (MSB) is decided by only one DT comparator. The design consumes 2.81 mW of power on average. The total area of the layout is 0.088 mm2. The figure of merit (FOM) is about 877 fJ/step. The research ends up with a fabricated chip with the design inserted into it.

A 12-bit SAR ADC with a reversible VCM-based capacitor switching scheme

A low-power 12-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a reversible VCM-based capacitor (RVC) switching scheme is presented in this paper. The switching power consumption of the proposed scheme is 95% and 62.3% lower than that of conventional and VCM-based capacitor switching schemes, respectively. The use of a segmented DAC structure reduces the size of the largest capacitor from 211 unit capacitors in the conventional capacitor array to 24 unit capacitors. This 75% reduction in the capacitor area decreases the settling time of the DAC capacitor network as well as requirements on the bandwidth and driving capability of the reference source VREF. An ADC prototype with an active area of 0.218 mm2is fabricated in 180-nm 1P6M CMOS process. With supply of 1.8 V and sampling rate of 10 MS/s, the ADC achieves a signal-to-noise and distortion ratio (SNDR) of 58.9 dB and consumes power of 0.36 mW, yielding a figure of merit (FOM) of 59.8fJ/conversion-step.

MODIFIED HIGH SPEED AND LOW POWER 32-BIT VEDIC MULTIPLIER DESIGN AND IMPLEMENTATION

–The multiplier speed is a significant feature as the multiplier forms an important part of many systems like FIR filters, microprocessors, DSPs etc. The multiplier is slow as compared to other parts of the system hence it is the speed determining factor of the system. An improvement in speed of the multiplier leads to an improvement in speed of the overall speed. The multiplier speed not only depends on the multiplication technique used it is also depends on the type of adder employed for the addition of the partial products. The proposedhigh speed and low power 32-bit Vedic multiplier architectures based on Vedic sutra namely, Urdhva-Triyag using Carry Save Adder(CSA) has been implemented.Among various methods of multiplication, recently Vedic multipliers are being more efficient. These sutras meant for fastercalculation.Urdhva-Triyag is more efficient than other multipliers with respect to speed. The most significant aspect of the Urdhva-Triyag sutra is, the developed multiplier generates allpartial products in one step. High speed adders are used in the architecture instead of conventional Ripple carry adders thereby reducing the delay further.Finally, the results are comparedwith conventional multipliers to show the efficiency in terms of speed.The effectiveness of theproposed method is synthesized and simulated using Xilinx tool using Verilog coding Software Tools:  Xilinx ISE 14.7 Tool Key Words:Vedic Multiplier, Urdhva-Triyagbhyam sutra, Ripple Carry Adder,Carry Save Adder.

Design and Implementation of High Speed and Low Power 12-bit SAR ADC using 22nm FinFET

Successive Approximation Register (SAR) Analog to Digital Converter (ADC) architecture comprises of sub modules such as comparator, Digital to Analog Converter and SAR logic. Each of these modules imposes challenges as the signal makes transition from analog to digital and vice-versa. Design strategies for optimum design of circuits considering 22nm FinFET technology meeting area, timing, power requirements and ADC metrics is presented in this work. Operational Transconductance Amplifier (OTA) based comparator, 12-bit two stage segmented resistive string DAC architecture and low power SAR logic is designed and integrated to form the ADC architecture with maximum sampling rate of 1 GS/s. Circuit schematic is captured in Cadence environment with optimum geometrical parameters and performance metrics of the proposed ADC is evaluated in MATLAB environment. Differential Non Linearity and Integral Non Linearity metrics for the 12-bit ADC is limited to +1.15/-1 LSB and +1.22/-0.69 LSB respectively. ENOB of 10.1663 with SNR of 62.9613 dB is achieved for the designed ADC measured for conversion of input signal of 100 MHz with 20dB noise. ADC with sampling frequency upto 1 GSps is designed in this work with low power dissipation less than 10 mW.

Construction a CO2 Incubator for Cell Culture with Capability of Transmitting Microwave Radiation.

Background:The objective of this study was to design and construct a CO2 incubator with nonmetallic walls and to investigate the viability of the cells and microwave irradiance inside this incubator.Methods:Because the walls of conventional incubators are made of metal, this causes scattering, reflection, and absorption of electromagnetic waves. We decided to build a nonmetallic wall incubator to examine cells under microwave radiation. Incubator walls were made using polyvinyl chloride and Plexiglas and then temperature, CO2 pressure, and humidity sensors were placed in it. Atmel® ATmega1284, a low-power CMOS 8-bit microcontroller, collects and analyzes the sensor information, and if the values are less or more than the specified limits, the command to cut off or connect the electric current to the heater or CO2 solenoid valve is sent. Using a fan inside the incubator chamber, temperature and CO2 are uniforms. The temperature of the points where the cell culture plates are placed was measured, and the temperature difference was compared. Ovarian cancer cells (A2780) were cultured in the hand-made and commercial incubators at different times, and cell viability was compared by the MTT method. Microwave radiation in the incubator was also investigated using a spectrum analyzer. The survival of cells after microwave irradiation in the incubator was measured and compared with control cells.Results:The data showed that there was no significant difference in temperature of different points in hand-made incubator and also there was no significant difference between the viability of cells cultured in the hand-made and commercial incubators. The survival of irradiated cells in the incubator was reduced compared to control cells, but this reduction was not significant.Conclusion:This incubator has the ability to maintain cells and study the effects of electromagnetic radiations on the desired cells, which becomes possible by using this device.

Design Analysis and Implementation of Automatic Fire Extinguishing System Using ATmega16 Microcontroller as Control

Aim: The aim of this research is to design an automatic fire detection and control.
 Methodology: The system consists of two sensors, microcontroller, buzzer and a pump/sprinkler. An LM35 integrated chip has been used as temperature sensor while MQ-2 gas sensor has been used as smoke sensor. All sensors are connected to the microcontroller through an input/output port. The controlling software for the whole system was designed in C programming language. The popular high performance, low power 8-bit microcontroller from the AVR family microcontrollers has been used. The system was finally tested by introducing fire parameters (smoke and temperature) close to the smoke and temperature detectors respectively. When the parameters go above the set level in the detectors, audio alarm, light indicator and pump/sprinkler were activated. The measured temperature of the system was compared with the reference temperature. 
 Results: The result showed that there was a mean deviation of 1.550C between the measured values and reference values which served as the control. 
 Conclusion: The constructed system is compact and easy to install. The constructed fire control device is quite cheap and affordable to every category of person.

Quantization and Deployment of Deep Neural Networks on Microcontrollers.

Embedding Artificial Intelligence onto low-power devices is a challenging task that has been partly overcome with recent advances in machine learning and hardware design. Presently, deep neural networks can be deployed on embedded targets to perform different tasks such as speech recognition, object detection or Human Activity Recognition. However, there is still room for optimization of deep neural networks onto embedded devices. These optimizations mainly address power consumption, memory and real-time constraints, but also an easier deployment at the edge. Moreover, there is still a need for a better understanding of what can be achieved for different use cases. This work focuses on quantization and deployment of deep neural networks onto low-power 32-bit microcontrollers. The quantization methods, relevant in the context of an embedded execution onto a microcontroller, are first outlined. Then, a new framework for end-to-end deep neural networks training, quantization and deployment is presented. This framework, called MicroAI, is designed as an alternative to existing inference engines (TensorFlow Lite for Microcontrollers and STM32Cube.AI). Our framework can indeed be easily adjusted and/or extended for specific use cases. Execution using single precision 32-bit floating-point as well as fixed-point on 8- and 16 bits integers are supported. The proposed quantization method is evaluated with three different datasets (UCI-HAR, Spoken MNIST and GTSRB). Finally, a comparison study between MicroAI and both existing embedded inference engines is provided in terms of memory and power efficiency. On-device evaluation is done using ARM Cortex-M4F-based microcontrollers (Ambiq Apollo3 and STM32L452RE).

A Low-Power 12-Bit 20 MS/s Asynchronously Controlled SAR ADC for WAVE ITS Sensor Based Applications.

A low power 12-bit, 20 MS/s asynchronously controlled successive approximation register (SAR) analog-to-digital converter (ADC) to be used in wireless access for vehicular environment (WAVE) intelligent transportation system (ITS) sensor based application is presented in this paper. To optimize the architecture with respect to power consumption and performance, several techniques are proposed. A switching method which employs the common mode charge recovery (CMCR) switching process is presented for capacitive digital-to-analog converter (CDAC) part to lower the switching energy. The switching technique proposed in our work consumes 56.3% less energy in comparison with conventional CMCR switching method. For high speed operation with low power consumption and to overcome the kick back issue in the comparator part, a mutated dynamic-latch comparator with cascode is implemented. In addition, to optimize the flexibility relating to the performance of logic part, an asynchronous topology is employed. The structure is fabricated in 65 nm CMOS process technology with an active area of 0.14 mm2. With a sampling frequency of 20 MS/s, the proposed architecture attains signal-to-noise distortion ratio (SNDR) of 65.44 dB at Nyquist frequency while consuming only 472.2 µW with 1 V power supply.

Design and Implementation of Low Power 32-bit Comparator

Comparator plays a vital role in many IC applications, Microprocessors, computer systems etc. Hence it is desirable to design a comparator block with low power consumption and high-speed performance. In this paper a novel architecture of 32-bit comparator using Complementary metal-oxide semiconductor logic is proposed and computed its delay and power metrics. Further it is compared with the full adder based 32-bit comparator. From the analysis we derive the comparison between proposed and the conventional comparator. The complete designing of architectures and their result analysis was done in cadence virtuoso tool at 180 nm technology. Simulation results show that there is reduce in power consumption of 90% when compared to the conventional full adder-based comparator.

An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC

A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18-μm 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as -0.4/0.54 and -0.81/0.89 LSB, respectively, where 1 LSB = 0.488 mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s.

Design and Implementation of Efficient 8-Bit SIPO Shift Register

Area and power are main design constraints in analog and digital circuits. In this paper, a low-power 8-bit shift register is implemented by using true phase single clock (TSPC) D- flip flop which is based on single clock and two clocked transistors. The proposed design successfully solves the long discharge path problem which is bound to occur in conventional type of D-Flip Flop. This paper describes 8 bit serial in parallel out (SIPO) shift register using True Single-Phase Clock(TSPC) technique which reduces an area in terms of transistor count by 85.29%.

Design of low power 16-bit counter with Programmable Combinational Logic and Integrated Clock Gating using 16-nm technology

ABSTRACT To demand high power back up by increasing the user’s need for applications in a single IC, the power dissipation takes place. The proposed two approaches are control Logic (CL) with Integrated Clock Gating (ICG) and Programmable Combinational Logic(PCL)and Gate Logic(GL) with ICG to achieve the low power and low dynamic leakage in 16-bit Counter. These approaches operate in different Logic to Generate/stop the clock for low-power digital circuits. The First approach of control Logic with ICG stops the clock only for single Most Significant Flip Flop Transistor. This approach consumes 1.6 mW and 15% more power savings than Existing. But the second approach only consumes 0.0261 mW power, which is 98% more power savings than a first proposed approach of CL with ICG and conventional counters. These dramatic boom power savings by stopping the clock for all redundant transition in Most Significant Flip Flop Transistors using PCL & GL with ICG. Analyse the second approach without ICG for 16-bit counter will consume 0.0334 mW, which consumes 21.96% high power than the presence of ICG in counter circuits. Moreover, the same proposed technique of the second approach applies for ISCAS’89 S444 circuits, which saves >90% power improvement than the conventional method and ordinary 16-bit counter-power analysis by the same technology, which consumes 42.42% high power than proposed low-power counter. The Low Power 16-bit counter design implementation using 16 nm Cadence Genustechnology, which attains the dynamic leakage with ICG is 0.170nW and without ICG is 0.177nW with an operating voltage of 0.8 V.

Spatial Confinement Effects of Embedded Nanocrystals on Multibit and Synaptic Properties of Forming Free SiO2-Based Conductive Bridge Random Access Memory

In this work we examine the position effect of embedded Pt nanocrystals (NCs) within a conductive bridge resistive switching memory (CBRAM) based on SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> which results in self-rectifying properties, low-voltage and more reliable operation. With this material configuration, we derive a large memory window, good spatial and temporal variability, robust pulse endurance and charge retention capabilities. Depending on the applied pulse characteristics we also exhibit low power 4-bit multilevel capabilities along with synaptic properties. The results are compared against a similar device without embedded NCs, gaining insights regarding the spatial confinement of silver nanofilaments by the presence of metallic NCs and its beneficial impact on device operation.

Leakage Power Minimization using IVC based GSA

The power management has become the major constraint while designing VLSI circuits as parameters like Area, Speed, etc. are critical to be optimized. In this work, a low power 16-bit ALU is designed to perform all arithmetic and logic operations. The present day super computers, mobile gadgets, calculators etc. are using low power ALU systems to perform their tasks. Especially, leakage power occupies major portion of power consumption in the CMOS circuits, as the process technology progresses. The objective of the research work is to reduce leakage power in maximum extent to run the ALU with low power. The proposed model has used IVC based leakage power reduction technique in standby mode by using Gravitational Search Algorithm (GSA). Input Vector Control (IVC) technique is found to be a better alternative in achieving low leakage as it is based on the effect of transistor stacking and it is highly preferred because of its independency over other technological parameters without performance overhead. The GSA locates MLV (Minimum Leakage Vector) in vector combinations of input test circuits of ALU. And then IVC forces the other vector combinations into MLV mode of a test circuit to reduce leakage power. The comparison study has been carried out with Genetic Algorithm (GA) and Particle Swarm Optimization (PSO) algorithm with various test circuits. Power analysis is conducted with GSA to ascertain better leakage reduction and also it locates MLV in less number of iterations. GSA takes only 13 iterations to reach its global space, whereas, PSO takes 62 iterations and GA takes 96 iterations to reach their global space. The simulations are carried out using the Xilinx platform with Verilog coding using PSPICE and MATLAB tools.

32-Bit One Instruction Core: A Low-Cost, Reliable, and Fault-Tolerant Core for Multicore Systems

Abstract Occurrences of both transient and permanent errors pose a major challenge in the wake of burgeoning growth in transistor density. Manufacturing defects and process variants lead to permanent faults, thereby lowering processor yields. In the arithmetic logic unit, single permanent faults result in the absolute failure of processors. Both low-energy neutrons and alpha particles from the cosmos induce transient errors by altering the state of the transistor. In wake of the implications, we postulate a new, reliable, fault-tolerant, low-cost 32-bit one instruction core (OIC) for a multicore system. “Low cost” here means low power and lower area. Notably, 32-bit OIC provides fault-free execution with triple redundant subtractors with one additional subtractor. It only executes one instruction called subleq repetitively in order to emulate the faulty instructions migrated into it by other cores. Hardware synthesis is undertaken to estimate leakage power, dynamic power, critical path delay, and area. The low-power 32-bit OIC consumes 1.3 mW, with a die area of 8,122 μm2. Apart from also adding performance overhead, 32-bit OIC outperforms its competitors with regard to reliability, area, power, and critical path delay. Additionally, the probabilistic estimate with link vulnerability factor—as a new parameter—is introduced to assess the effect of soft errors or transient faults on interconnect wires, which are then quantitatively analyzed to illuminate the resilience of 32-bit OIC hardware structure. Additionally, we propose new design alternatives (including existing ones) for heterogeneous multicore systems in order to develop low-cost solutions with a primary focus on reliability.