Low-power 1-bit Full Adder Research Articles

High-Performance 1-Bit Full Adder With Excellent Driving Capability for Multistage Structures

In this letter, a low-power 1-bit full-adder (FA) cell is proposed based on the transmission gate (TG) to attain a special module for generating full-swing Carry output. The cell benefits from the high driving capability for both Sum and Carry outputs when embedding in multistage structures like ripple-carry adders (RCAs), compressors, and multipliers. The proposed TG-based FA has a total die area of 60.02 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}^{2}$ </tex-math></inline-formula>, while the average power, delay, and power-delay-product (PDP) are 10.829 <inline-formula> <tex-math notation="LaTeX">$\mu \text{W}$ </tex-math></inline-formula>, 3.1954 ns, and 34.603 fJ, respectively. The results introduce the FA cell as an efficient gate for integrated circuits (ICs).

Performances Analysis of High-Speed Low-Power 1-bit Full Adder

Performances Analysis of High-Speed Low-Power 1-bit Full Adder

Design of Two High Performance 1-Bit CMOS Full Adder Cells

bit full adder is a very great part in the design of application particular integrated circuits. Power consumption is one of the most significant parameters of full adders. Therefore reducing power consumption in full adders is very important in low power circuits. In this paper, we propose two new structures of hybrid full adders. The first full adder implemented by combining the Swing Restored Lass-transistor Logic and Branch-Based Logic that called, SRPL-BBL cell and the second full adder implemented by combining the Gate-Diffusion Input technique and Majority function that called, GDI-Majority cell. All of the capacitors in this paper replaced with MOSCAP. Simulation results performed by HSPICE in TSMC 0.13 μm CMOS process. The results indicate the superiority the proposed full adders against several low power 1-bit full adder cells in terms of delay, power consumption, and power delay product (PDP).

An energy efficient full adder cell for low voltage

This paper presents an area efficient, high-speed and ultra low power 1-bit full adder that uses only 9 transistors. It works based on majority function and MOS capacitors. Because of the simple structure of the proposed design and reduced transistor counts, a very low power full adder is realized. It also can work more reliably at ultra low supply voltage in comparison with the previous designs. The circuit being studied is optimized for energy efficiency at 0.18-µm CMOS process technology. The adder cell is compared to four standard adders based on power consumption, speed and power delay product. Intensive simulation runs on HSPICE shows that the new adder has more than 44% in power savings over conventional CMOS adder and is 10% faster.

On the design of low power 1-bit full adder cell

A 1-bit full adder cell based on majority function is designed and simulated. In this design the time consuming XOR gates are eliminated. Low-power consumption is targeted in implementation of our design. The circuit being studied is optimized for energy efficiency at 0.18-µm CMOS process technology. The new circuit has been compared to the previous work based on power consumption, speed and power delay product (PDP). HSPICE and Cadence simulations show that the proposed adder can work more reliably at different range of supply voltage. The proposed design has the best PDP in comparison with the others.

Two new low-power Full Adders based on majority-not gates

Two novel low-power 1-bit Full Adder cells are proposed in this paper. Both of them are based on majority-not gates, which are designed with new methods in each cell. The first cell is only composed of input capacitors and CMOS inverters, and the second one also takes advantage of a high-performance CMOS bridge circuit. These kinds of designs enjoy low power consumption, a high degree of regularity, and simplicity. Low power consumption is targeted in implementation of our designs. Eight state-of-the-art 1-bit Full Adders and two proposed Full Adders are simulated using 0.18μm CMOS technology at many supply voltages. Simulation results demonstrate improvement in terms of power consumption and power-delay product (PDP).