Low Phase Noise Frequency Synthesizer Research Articles

A Low Phase Noise Frequency Synthesizer with a Fourth-Order RLC Loop Filter

The current work employs the HMC830 phase-locked loop chip to design a frequency synthesizer operating in the L-band. The frequency synthesizer can provide a local oscillation signal for the RF receiver front end. This article employs the phase-locked synthesis technique to describe the design scheme. Due to the advantages of the passive loop filters, such as simplicity, low cost, and low phase noise, a passive fourth-order RLC loop filter is proposed to improve the output signal quality and reduce phase noise. The performance of this loop filter is compared with the passive fourth-order RC loop filter. The effects of these two loop filters on phase noise, loop capture time, and spur suppression are analyzed. Subsequently, the design scheme, simulation analysis, and test results of the frequency synthesizer are presented under these two loop filters. The test results indicate that the passive fourth-order RLC loop filter outperforms the passive fourth-order RC loop filter; its output signal phase noise is higher than −100 dBc/Hz@1 kHz, loop capture time is less than 100 us, and spur suppression is better than 60 dBc. This frequency synthesizer can provide high-performance local oscillation signals for wireless communication equipment such as transmitters and receivers. It meets the application requirements of many radio communication circuit structures and has good application prospects.

A frequency multiplier for reference frequency in frequency synthesizer systems

A low jitter frequency multiplier, which requires less power, area, and design complexity than reference multiplying PLL or DLL circuits can be used to generate the reference frequency for a low phase noise frequency synthesizer. This paper proposes a mixed signal solution based on the fact that the average DC value of a signal is proportional to its duty cycle. The solution uses a feedback loop with coarse and fine delay resolution to generate a $$90^{\circ }$$ phase shifted clock that is used to produce a doubled frequency signal with 50% duty cycle. This method can be used to multiply the input frequency of 40 MHz by multiples of 2, up to 16. The design is implemented in 65 nm UMC CMOS process. Operating from 1.2-V supply, it dissipates 0.46 to 1.2 mA at output frequencies 80–640 MHz, achieving − 162.3 and − 139 dBc/Hz phase noise at 1 MHz offset, respectively.

Low Phase Noise Frequency Synthesis for Ultrastable $X$ -Band Oscillators

In this letter, the design of a low phase noise frequency synthesizer is presented. The synthesizer was designed to produce four frequencies: 10 MHz, 100 MHz, 1 GHz and 10 GHz. The 1-GHz signal is produced by frequency division whereas the 100-MHz output is generated by phase-locking a low phase noise oscillator to the 1-GHz signal, hence significantly reducing its phase noise. Both residual and total phase noise measurements are presented.

낮은 위상잡음 특성을 갖는 0.5~4 GHz 주파수 합성기 설계 및 제작

낮은 위상잡음 특성을 갖는 0.5~4 GHz 주파수 합성기 설계 및 제작

A 220–1100 MHz low phase-noise frequency synthesizer with wide-band VCO and selectable I/Q divider

This paper presents a low phase-noise fractional-N frequency synthesizer which provides an in-phase/quadrature-phase (I/Q) signal over a frequency range of 220–1100 MHz for wireless networks of industrial automation (WIA) applications. Two techniques are proposed to achieve the wide range. First, a 1.4–2.2 GHz ultralow gain voltage-controlled oscillator (VCO) is adopted by using 128 tuning curves. Second, a selectable I/Q divider is employed to divide the VCO frequency by 2 or 3 or 4 or 6. Besides, a phase-switching prescaler is proposed to lower PLL phase noise, a self-calibrated charge pump is used to suppress spur, and a detect-boosting phase frequency detector is adopted to shorten settling time. With a 200 kHz loop bandwidth, lowest measured phase noise is −106 dBc/Hz at a 10 kHz offset and −131 dBc/Hz at a 1 MHz offset. Fabricated in the TSMC 0.18 μm CMOS process, the synthesizer occupies a chip area of 1.2 mm2, consumes only 15 mW from the 1.8 V power supply, and settles within 13.2 μs. The synthesizer is optimized for the WIA applications, but can also be used for other short-range wireless communications, such as 433, 868, 916 MHz ISM band applications.

KU-BAND 저 위상잡음 주파수 합성기 설계에 관한 연구

In the proposed paper, we designed low phase noise frequency synthesizer for Ku-band. The proposed up-mixing frequency synthesizer consists of narrow local oscillation part and variable frequency oscillation part. To improve the phase noise of frequency synthesizer, we analyze how the configuration of frequency synthesizer affect the phase noise. The implemented frequency synthesizer reduce the phase noise. The phase noise is -95.18dBc/Hz at 7kHz frequency offset in 16GHz and -94.27dBc/Hz at 7kHz frequency offset in 16.125GHz.

A low phase noise and low spur PLL frequency synthesizer for GNSS receivers

A low phase noise and low spur phase locked loop (PLL) frequency synthesizer for use in global navigation satellite system (GNSS) receivers is proposed. To get a low spur, the symmetrical structure of the phase frequency detector (PFD) produces four control signals, which can reach the charge pump (CP) simultaneously, and an improved CP is realized to minimize the charge sharing and the charge injection and make the current matched. Additionally, the delay is controllable owing to the programmable PFD, so the dead zone of the CP can be eliminated. The output frequency of the VCO can be adjusted continuously and precisely by using a programmable LC-TANK. The phase noise of the VCO is lowered by using appropriate MOS sizes. The proposed PLL frequency synthesizer is fabricated in a 0.18 μm mixed-signal CMOS process. The measured phase noise at 1 MHz offset from the center frequency is −127.65 dBc/Hz and the reference spur is −73.58 dBc.

YTO를 이용한 광대역 저 위상 잡음 주파수 합성기 설계 및 제작

The low phase noise and wideband frequency synthesizer has been designed by using YTO. Offset PLL structure is used for reducing a division ratio of feedback loop. The phase noise modeling is applied to optimize loop filter of PLL and YTO module. And DDS is used as reference signal of frequency synthesizer for fine resolution. The fabricated wideband frequency synthesizer has the output frequency of 3.2 GHz to 6.8 GHz, phase noise of -107 dBc/Hz at 10 kHz offset from the carrier and frequency resolution of 1 Hz. The measured phase noise is well agreed with the simulated one.

A Low Phase Noise Ring-VCO Based PLL Using Injection Locking for ZigBee Applications

A low power low phase noise frequency synthesizer with subharmonic injection locking is proposed for ZigBee applications. The PLL is based on a ring VCO to decrease area and production cost. In order to improve phase noise performance, a high frequency injection signal of which frequency varies with channel number is used. The circuit is designed in TSMC 0.18 μm CMOS technology and simulated in ADS (Advanced Design System). The phase noise at 3.5 and 10 MHz offsets is -116 and -118 dBc/Hz, respectively, and total circuit consumes 2.2 mA current.

고주파용 소형 저 위상잡음 주파수 합성기 설계에 관한 연구

In this paper, we designed low phase noise frequency synthesizer with compact size for High frequency band (Ku-band). The paper addresses merits and demerits of single loop and dual loop frequency synthesizer. The phase noise characteristics of the phase-locked loop frequency synthesizer were predicted based on the analysis for phase noise contribution of noise sources. The proposed model in this paper more accurately predicts the low phase noise frequency synthesizer with compact size for high frequency band.

A 2.4GHz low phase noise frequency synthesizer for WiMAX applications

This paper presents a low phase noise frequency synthesizer for WiMAX applications. The operating frequency of the proposed design ranges from 2.2GHz to 2.4GHz with a 1.25MHz spacing for the 1.25MHz to 40MHz channel bandwidth. The proposed VCO suppresses the phase noise effectively by adopting the Q-enhancement technique, the memory reduced tail current, and a noise filter. The high speed frequency divider is implemented by an improved TSPC D-flip-flop. The proposed design is fabricated in a TSMC 0.18µm CMOS 1P6M process. The measured phase noise is -118Bc/Hz at an offset of 1MHz from the center frequency. The fabricated chip consumes 25.5mW with a 1.5V supply and occupies a 1.1mm2 die area.

Wideband Frequency Synthesizer at X/Ku Band by Mixing and Phase Locking of Half Frequency Output of VCO

A wideband low phase noise frequency synthesizer at X/Ku band has been developed by using phase locking and mixing technique at half frequency of voltage controlled oscillator (VCO). The half frequency output signal of the VCO is down converted by a balanced mixer at C band to obtain an intermediate frequency (IF) signal used for phase locking of the VCO. An ultra low phase noise local signal source at 6 GHz is developed with a frequency multiplying chain driven by a 100 MHz oven controlled crystal oscillator (OCXO). Coupling circuit outside the VCO chip to the mixer does not need to be specially designed, which is beneficial to simplify the circuit scheme and improve the phase noise performance. Measurement results show that the phase noise of the output signal at 10.6 GHz to 11.8 GHz and 12.3 GHz to 13.0 GHz is better than −102 dBc/Hz at 10 kHz away form the carrier center. This frequency synthesizer can be used as local signal source or driving source for the development of wideband millimeter-wave frequency synthesizer systems.