Low Off-state Leakage Current Research Articles

Supramolecular Transistors with Quantum Interference Effect.

The charge transport through supramolecular junctions exhibits unique quantum interference (QI) effects, which provide an opportunity for the design of supramolecular transistors. Benefiting from the configuration dependence of QI, configuration control of the supramolecular assemblies to demonstrate the QI features is a key but challenging step. In this work, we fabricated the supramolecular transistors and investigated the charge transport through the conducting channel of the individual π-stacked thiophene/phenylene co-oligomers (TPCOs) using the electrochemically gated scanning tunneling microscope break junction technique. We controlled the configuration of the supramolecular channel and switched the QI features between the anti-resonance and resonance states of the supramolecular channels. We observed the supramolecular transistor with its on/off ratio above 103 (∼1300), a high gating efficiency of ∼165 mV/dec, a low off-state leakage current of ∼30 pA, and the channel length scaled down to <2.0 nm. Density functional theory calculations suggested that the QI features in π-stacked TPCOs vary depending on the supramolecular architecture and can be manipulated efficiently by fine-tuning the supramolecular configurations. This work reveals the potential of the supramolecular channels for molecular electronics and provides a fundamental understanding of intermolecular charge transport.

True Nonvolatile High-Speed DRAM Cells Using Tailored Ultrathin IGZO.

Severe power consumption in the continuous scaling of Silicon-based dynamic random access memory (DRAM) technology quests for a transistor technology with a much lower off-state leakage current. Wide bandgap amorphous oxide semiconductors, especially indium-gallium-zinc-oxide (IGZO)exhibit many orders of magnitude lower off-state leakage. However, they are typically heavily n-doped and require negative gate voltage to turn off, which prevents them from true nonvolatile operation. The efforts on doping density reduction typically result in mobility degradation and high Schottky barriers at contacts, causing severe degradation of on-current and operation speed of the DRAM cells. Here, high-speed true nonvolatile DRAM cells are successfully demonstrated by deep suppression of doping density in the IGZO channel using in situ oxygen ion beam treatment and ohmic contact engineering by inserting a thin In-rich indium-tin-oxide (ITO) at contact regions. A record high on-current of 40µA µm-1 at a large positive threshold voltage of 1.78V enables the first true nonvolatile DRAM with the fastest write speed of 10ns and data retention up to 25 h under power interruption, five orders of magnitude higher than the previously projected values.

Charge Trapping and Emission Properties in CAAC-IGZO Transistor: A First-Principles Calculations.

The c-axis aligned crystalline indium-gallium-zinc-oxide field-effect transistor (CAAC-IGZO FET), exhibiting an extremely low off-state leakage current (~10-22 A/μm), has promised to be an ideal candidate for Dynamic Random Access Memory (DRAM) applications. However, the instabilities leaded by the drift of the threshold voltage in various stress seriously affect the device application. To better develop high performance CAAC-IGZO FET for DRAM applications, it's essential to uncover the deep physical process of charge transport mechanism in CAAC-IGZO FET. In this work, by combining the first-principles calculations and nonradiative multiphonon theory, the charge trapping and emission properties in CAAC-IGZO FET have been systematically investigated. It is found that under positive bias stress, hydrogen interstitial in Al2O3 gate dielectric is probable effective electron trap center, which has the transition level (ε (+1/-1) = 0.52 eV) above Fermi level. But it has a high capture barrier about 1.4 eV and low capture rate. Under negative bias stress, oxygen vacancy in Al2O3 gate dielectric and CAAC-IGZO active layer are probable effective electron emission centers whose transition level ε (+2/0) distributed at -0.73~-0.98 eV and 0.69 eV below Fermi level. They have a relatively low emission barrier of about 0.5 eV and 0.25 eV and high emission rate. To overcome the instability in CAAC-IGZO FET, some approaches can be taken to control the hydrogen concentration in Al2O3 dielectric layer and the concentration of the oxygen vacancy. This work can help to understand the mechanisms of instability of CAAC-IGZO transistor caused by the charge capture/emission process.

An Artificial Neural Network Implemented Using Parallel Dual-Gate Thin-Film Transistors

Implementing in-memory computation, an artificial neural network (ANN) consisting of thin-film transistors (TFTs) monolithically integrated in each unit of an array of capacitors is constructed. Both single-gate and parallel, dual-gate (DG) TFTs are deployed. The capacitors and the DG TFTs serve as the respective memory and computational elements. The DG TFT offers the capability of amplifying a weak but relevant input signal and suppressing a strong but irrelevant input signal across a synaptic gap, and the storage of charge on the capacitor is pseudostatic because of the exceptionally low OFF-state leakage current of the accompanying address TFT built on a metal–oxide semiconductor. The feasibility of such an ANN is demonstrated using a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4\times6$ </tex-math></inline-formula> array for classifying a specific set of Tetris patterns.

Polarization modulation of 2DEG toward plasma-damage-free GaN HEMT isolation

GaN electronics have hinged on invasive isolation such as mesa etching and ion implantation to define device geometry, which, however, suffer from damages, hence potential leakage paths. In this study, we propose a new paradigm of polarization isolation utilizing intrinsic electronic properties, realizing in situ isolation during device epitaxy without the need of post-growth processing. Specifically, adjacent III- and N-polar AlGaN/GaN heterojunctions were grown simultaneously on the patterned AlN nucleation layer on c-plane sapphire substrates. The two-dimensional electron gas (2DEG) was formed at III-polar regions but completely depleted in N-polar regions, thereby isolating the 2DEG channels with a large 3.5 eV barrier. Structures of polarization-isolated high electron mobility transistors (PI-HEMTs) exhibit significantly reduced isolation leakage currents by up to nearly two orders of magnitude at 50 V voltage bias compared to the state-of-the-art results. Aside from that, a high isolation breakdown voltage of 2628 V is demonstrated for the PI-HEMT structure with 3 μm isolation spacing, which is two-times higher than a conventional mesa-isolation HEMT. Moreover, the PI-HEMT device shows a low off-state leakage current of 2 × 10−8 mA/mm with a high Ion/Ioff ratio of 109 and a nearly ideal subthreshold slope of 61 mV/dec. This work demonstrates that polarization isolation is a promising alternative toward the plasma-damage-free isolation for GaN electronics.

Fabrication and characterization of GaN-based nanostructure field effect transistors

Two different types of GaN-based nanostructure FETs, such as FinFETs and gate-all-around (GAA) nanowire FETs, have been investigated along with discussing their important performances for a possible new application. The GaN-based FinFETs have better electrostatic control compared to conventional planar-type GaN-based HEMTs, which offers great performance improvement such as very low off-state leakage current, high breakdown voltage, high linearity with broad transconductance. Recent investigation demonstrated that an appropriately designed AlGaN/GaN-FinFETs could exhibit low saturation drain voltage and very fast switching characteristics with subthreshold swing of sub-60 mV dec, which indicates that they can be a promising candidate for low voltage/power logic application. GAA GaN nanowire FETs have even better electrostatic control and exhibit excellent device performances showing their potential low voltage/power logic applications. For clear understanding of the device performances, simulation including two models concerning the multi-level trapping effects and the self-heating effects has been conducted, which leads to good agreement with the experimental results. Negative transconductance and offset-like output characteristics, observed in the narrow nanowire devices, have been well explained using the deep trapping effect and the built-in potential at ohmic contact. Scaling of the nanowire FET has been implemented such as channel length, doping concentration, and diameter of nanowire, which helps to predict further improvement of the device performance.

Segmented Drain Engineered Tunnel Field Effect Transistor for Suppression of Ambipolarity

In this paper, a new Si0.6Ge0.4/Si heterostructure tunneling field-effect transistor with segmented drain (SiGe/Si SD TFET) is proposed and simulated by Silvaco ATLAS simulator. The drain segmentation increases the tunneling barrier width at the drain/channel interface and hence reduces ambipolar current (Iamb) considerably. Moreover, the amalgam of Si0.6Ge0.4 source and silicon channel allows much improved On-state current (Ion) with lower Off-state leakage current (Ioff). The presence of high bandgap silicon material keeps the lower recombination rate of the carriers in the channel region, thus provides a much higher Ion/Ioff ratio of 5.64 × 1011. The segmented drain exhibits more than 4-decades improvement in Iamb without affecting Ion and Ioff. The thickness and doping profile of the segmented drain region are calibrated to achieve a higher Ion/Iamb ratio of 3.29 × 109 with an average subthreshold swing (SS) of 42 mV/decade. The investigation is further extended by considering the interface trap charges (ITCs) at the HfO2/Si interface for different positive and negative density values.

Multi-Level Memory Comprising Low-Temperature Poly-Silicon and Oxide TFTs

In this letter, a new multi-level memory cell using low-temperature polycrystalline silicon and oxide (LTPO) thin-film transistor (TFT) backplane is proposed. The multi-bit data storage can be achieved with a simple structure of two transistors and a capacitor, which controls the threshold voltage of a memory cell transistor exactly. In a memory cell, the low-temperature polycrystalline silicon (LTPS) TFT provides excellent stability against bias stress or current stress. In addition, the oxide semiconductor TFT enables the long-term data storage by virtue of its extremely low off-state leakage current. The proposed memory is fabricated with the LTPO TFT process which includes p-type LTPS and n-type oxide TFTs. Furthermore, the implementation of the multi-level property is successfully verified by measured results.

Subthreshold Characteristics of AlGaN/GaN MIS-FinFETs with Controlling Threshold Voltages

AlGaN/GaN metal-insulator-semiconductor field-effect transistors with fin structures (AlGaN/GaN MIS-FinFETs) were fabricated and characterized by changing fin width and using different dielectric layers. The FinFET with 20 nm-thick SiO2 dielectric layer exhibits a very small subthreshold swing (SS) of 56 mV/decade. However, the threshold voltage of the device is too low to ensure low off-state leakage current (at the gate voltage of 0 V), even though the fin width of the device is reduced to 30 nm, which would not meet the requirement for low standby power consumption. On the other hand, the FinFET with a 10 nm-thick Al2O3 dielectric layer and a much wider fin width of 100 nm shows normally-off operation with a threshold voltage of 0.8 V, SS of 63 mV/dec, and very low off-state current of 1 nA/mm. When the fin width is reduced to 40 nm, the threshold voltage of the FinFET is increased to 2.3 V and the SS is decreased to 52 mV/decade. These excellent switching performances convince us that the FinFETs might be promising either for low voltage logic or for efficient power switching applications. The observed SS values, which are smaller than the theoretical Boltzmann limit (60 mV/decade), can be explained by the concept of the voltage-dependent effective channel width.

Deposition of c-Axis Aligned Crystalline InGaZnO by Mist Atmospheric Pressure Chemical Vapor Deposition for Thin-Film Transistor Applications

This study uses mist atmospheric pressure chemical vapor deposition with deposition/annealing cyclic method to grow ${c}$ -axis aligned crystalline (CAAC) InGaZnO. The material characteristics of the CAAC-InGaZnO are analyzed by X-ray diffraction, X-ray photoelectron spectroscopy, photoluminescence, and an ellipsometer to determine the crystal structure, oxygen deficiency, trap energy level, and energy bandgap. The CAAC-InGaZnO thin-film transistor (TFT) shows better electrical performance than the one based on amorphous InGaZnO, including higher field-effect mobility (90.4 cm $^{2}\,\,\text{V}^{-1}\,\,\text{s}^{-1}$ ), lower OFF-state leakage current (16 pA), steeper subthreshold swing (86 mV/dec), and higher on/off current ratio (>1010). Moreover, the negative bias illumination stress (NBIS) test is used to estimate the stability of the TFT. The threshold voltage of the present CAAC-InGaZnO TFT changes −0.4 V when the TFT is stressed for 10 000 s.

Performance analysis of HfO2/InAlN/AlN/GaN HEMT with AlN buffer layer for high power microwave applications

We present a performance enhancement evaluation of n + doped graded InGaN drain/source region-based HfO 2 /InAlN/AlN/GaN/AlN on SiC metal-oxide-semiconductor high electron mobility transistor (MOS-HEMTs) with a T-shaped gate. Impact on the device characteristics with the inclusion of a HfO 2 surface passivation layer and an AlN buffer layer in the MOS-HEMT structure as a performance booster has been analyzed for the HEMT device with 30 nm gate length using Silvaco ATLAS TCAD. The proposed MOS-HEMT exhibits an outstanding performance, with an enhanced power gain cut-off frequency (f max ) of 366 GHz, a current gain cut-off frequency (f t ) of 426 GHz, and a off-state breakdown voltage (V br ) of 81 V. The high -k (high permittivity) HfO 2 based metal oxide semiconductor HEMT device experiences a low off-state gate leakage current (I g ~ 10 −11 A/mm) and a high I on /I off ratio of 10 9 . The InAlN/GaN/AlN heterostructures demonstrate improved two-dimensional electron gas (2DEG ~ 5.3 × 10 13 cm −2 ), carrier mobility (μ) of 1256 Cm 2 /V-s and drain current density of (I ds ) 2.7 A/mm. A large signal analysis performed at 30 GHz yielded a maximum of 28% power-added efficiency. The high JFoM of 34.506 THz V (Johnson Figure of Merit = f t × V br ) and (f t .f max ) 1/2 of 394.86 GHz indicate the potential applicability of the HfO 2 /InAlN/GaN MOS-HEMTs in high-frequency and high-power applications.

Breakdown Enhancement and Current Collapse Suppression in AlGaN/GaN HEMT by NiOX/SiNX and Al2O3/SiNX as Gate Dielectric Layer and Passivation Layer

We propose two kinds of stacked materials that effectively yield low drain off-state leakage current, high off-state breakdown voltage and low current collapse simultaneously in AlGaN/GaN HEMT. The two kinds of stacked materials, which is NiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> respectively, act as gate dielectric layer and passivation layer for the devices. The NiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> are prepared through depositing Ni and Al thin film by electron beam evaporation and then annealing in O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> ambient by rapid thermal processing. The SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> is deposited by plasma-enhanced chemical vapor deposition. Compared to the single SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> layer, the NiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> stack layer and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> stack layer can distinctly reduce the drain off-state leakage current of devices. Meanwhile, high off-state breakdown voltage is also achieved. The off-state breakdown voltage in the devices with NiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> stack layer and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> stack layer are 52% and 36% higher than that of the devices with single SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> layer respectively. Especially, the current collapse under 200 V stress bias is reduced by 90% and 58% in the devices with NiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> stack layer and Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> stack layer compare to the devices with single SiN <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">X</sub> layer respectively.

A novel high-performance fold I shaped junctionless FinFET

ABSTRACT In this article, a novel high-performance fold I shaped junctionless FinFET (FIS JL FinFET) is proposed. Compared to conventional JL FinFETs, the proposed FIS JL FinFET can realise lower off-state leakage current, lower parasitic capacitance while ensuring no degradation of the subthreshold swing. The electrical properties of the FIS JL FinFET have been extensively investigated through comprehensive discussions of the influences resulting from gate geometry engineering.

Reverse-Conducting Normally-OFF Double-Channel AlGaN/GaN Power Transistor With Interdigital Built-in Schottky Barrier Diode

Low-loss reverse-conducting normally- OFF double-channel AlGaN/GaN power transistor with the built-in Schottky barrier diode (SBD) has been systematically studied. This device features the MOS-gate section and SBD-anode section paralleled to an interdigital layout along the gate width direction. A common access region that conducts current at both forward and reverse ON-states is employed, which is beneficial to reduce the conduction loss. With a MOS-HEMT/SBD finger width of ${4}~\mu \text{m}/2~\mu \text{m}$ and a total width ratio of 2:1, the device exhibits a threshold voltage of +0.8 V at a drain current of ${10}~\mu \text{A}$ /mm and a low forward ON-resistance of $12.1~\Omega \cdot \text {mm}$ . The Schottky metal contacts 2-DEG directly, which results in a low reverse turn-on voltage of −0.6 V (at −1 mA/mm) and low reverse ON-state voltage of −1.7 V (at −50 mA/mm). A leakage suppression MOS field plate (FP) is applied to shield the Schottky contact from the strong electric field, leading to a low OFF-state leakage current of 14 nA/mm at +100-V drain bias and a high breakdown voltage (BV) of +698 V. The finger width and the number of fingers should be optimized. A narrow finger width benefits the current sharing at the access region, while the increasing number of fingers introduces more Schottky depletion regions along the gate width direction that degrade ${R}_{ \mathrm{\scriptscriptstyle ON}}$ .

200°C normally off AlGaN/GaN MISFET with 321 mA/mm drain current density and 1055 V breakdown voltage

A high-performance normally off recess-gated aluminium gallium nitride (AlGaN)/GaN metal–insulator–semiconductor field-effect transistor (MISFET) is successfully demonstrated with operation temperature of 200°C which was fabricated by using a self-terminating gate recess etching technique. At 200°C, by employing a high-quality aluminium oxide/silicon nitride bilayer as gate dielectrics, the fabricated device exhibits a high threshold voltage of 4.5 V, a high drain current density of 321 mA/mm, a low off-state leakage current of 20 μA/mm as well as a high on/off current ratio of ∼106. Furthermore, a high forward gate breakdown voltage of 23.6 V (∼7.9 MV/cm) and an off-state breakdown voltage as high as 1055 V are obtained in the fabricated device, both of which, as far as it is known, is the highest reported value in normally off GaN devices operated at 200°C. The high threshold voltage, large drain current density, low off-state leakage current, high gate breakdown voltage as well as high off-state breakdown voltage make this normally off recess-gated AlGaN/GaN MISFET very suitable for high-temperature power switch applications.

A ${c}$ -Axis-Aligned Crystalline In-Ga-Zn Oxide FET With a Gate Length of 21 nm Suitable for Memory Applications

We fabricated a field-effect transistor (FET) with a gate length of 21 nm whose channel material is a c-axis-aligned crystalline In-Ga-Zn oxide (CAAC-IGZO). A CAAC-IGZO FET with a gate length of 21 nm has an extremely low off-state leakage current, a practical driving capability, and tolerance against high temperatures. CAAC-IGZO FETs enable low-power integrated circuits, such as logic and memory in high-temperature environments. Performance estimation of a memory cell using the CAAC-IGZO FET with a gate length of 21 nm revealed that a write time of less than 1 ns and a data retention time of more than 1 h would be possible at 85 °C.

Impact of Zirconium Doping on Steep Subthreshold Switching of Negative Capacitance Hafnium Oxide Based Transistors

In this work, it is demonstrated that the negative capacitance effect of ferroelectric Hf1−xZrxO2 transistor is highly correlated with Zr doping concentration. A steep subthreshold swing of 40 mV/decade, a low off‐state leakage current of 190 fA μm−1, and a large on/off current ratio of &gt;107 can be simultaneously achieved in optimized negative capacitance Hf1−xZrxO2 transistor. Besides, the Zr diffusion issue and non‐ferroelectric phases significantly affect the multi‐domain switching of polycrystalline Hf1−xZrxO2. Therefore, an appropriate amount of Zr substitution is more favorable for both boosting ferroelectric and implementing the negative capacitance switch.

Growth of AlGaN/GaN heterostructure with lattice-matched AlIn(Ga)N back barrier

AlGaN/GaN heterostructures were successfully grown with the AlIn(Ga)N back barrier at 900 °C. However, the atomic composition of the AlIn(Ga)N layer was strongly dependent on the growth pressure, which resulted in a different lattice constant of the layer. The AlIn(Ga)N back barrier grown at 400 torr was almost lattice-matched to GaN layer. The AlGaN/GaN heterostructures with 10 and 15 nm-thick AlIn(Ga)N back barrier exhibited improved 2-DEG properties, compared to those of the conventional AlGaN/GaN heterostructure without the back barrier. The high electron mobility transistors (HEMTs) fabricated on the AlGaN/GaN heterostructure with a 15 nm-thick AlIn(Ga)N back barrier exhibited a very low off-state leakage current of ∼2 × 10−7 A/mm which is about 1 order lower in magnitude than the value of the device without the back barrier. The AlIn(Ga)N back barrier is a promising candidate as an alternative to conventional AlGaN and InGaN back barrier.

Al0.3Ga0.7N/GaN (10 nm)/Al0.1Ga0.9N HEMTs With Low Leakage Current and High Three-Terminal Breakdown Voltage

In this work, we presented a high performance AlGaN/GaN/AlGaN double heterostructure HEMT with a 10 nm channel layer and an Al0.1Ga0.9N back barrier layer. The fabricated devices exhibited an extremely low off-state drain leakage current of ${I}_{ {\scriptscriptstyle {\text{ON}}}}/{I}_{ {\scriptscriptstyle {\text{OFF}}}}$ ) of up to 1010 and a subthreshold swing (SS) of 63 mV/dec were attained due to the reduced leakage current and enhanced electron confinement. The presented devices with a gate-drain spacing ( ${L}_{\text {GD}}$ ) of $22~\mu \text{m}$ exhibited a soft breakdown voltage ( ${V}_{\text {BR}}$ ) of 1860 V with the criteria of $0.1~\mu \text{A}$ /mm and a hard ${V}_{\text {BR}}$ of 2009 V combined with a specific on-resistance ( ${R}_{ {\scriptscriptstyle {\text{ON}}}, \text {sp}}$ ) of 10.6 $\text{m}\Omega \!\cdot \! \text {cm}^{{2}}$ . Moreover, excellent high-temperature values for ${I}_{ {\scriptscriptstyle {\text{ON}}}}/{I}_{ {\scriptscriptstyle {\text{OFF}}}}$ , SS, and ${V}_{\text {BR}}$ were also attained. These results demonstrate a promising potential of the proposed devices for high power applications.

Low-Dispersion, High-Voltage, Low-Leakage GaN HEMTs on Native GaN Substrates

In this paper, the advantages of GaN high electron mobility transistors (HEMTs) grown on native GaN over GaN/Si or GaN/sapphire substrates are investigated and correlated with epitaxial material quality. Transmission electron microscopy plan-view and cross-sectional analyses of GaN/GaN reveal dislocation densities below ${1} \times {10}^{{6}}$ cm−2, which is at least three orders of magnitude lower than that of GaN/Si or GaN/sapphire. In the case of GaN/Si, the dislocations not only originate from the substrate/nucleation layer interface, but also the strain relief and isolation buffer stacks are main contributors to the dislocation density. GaN/GaN HEMTs show superior electrical and thermal performance and feature three orders of magnitude lower OFF-state leakage. The current collapse (also referred to as current dispersion or $R_{ \mathrm{\scriptscriptstyle ON}}$ -increase) after stress bias is less than 15% compared with 50% in the case of GaN/Si. A 2% drop of the ON-state current due to self-heating in dc operation when compared with 13% and 16% for GaN/Si and GaN/sapphire, respectively. The GaN/Si thermal performance becomes comparable to that of GaN/GaN only after substrate removal. Therefore, GaN/GaN provides high ON-state current, low OFF-state leakage current, minimal current collapse, and enhanced thermal power dissipation capability at the same time, which can directly be correlated with the absence of high dislocation density.