Variable Gain Low Noise Amplifier Research Articles

Design and optimization of variable gain LNA for IoT applications using meta-heuristics search algorithms

In this paper, Variable Gain LNA (VG-LNA) parameters are optimized using the Particle Swarm Optimization (PSO), Firefly Algorithm (FA), and Genetic Algorithm (GA). A comparison of the three optimization techniques has been done and FA is depicting better results over GA and PSO. VG-LNA is composed of a Complementary Common Gate (CCG) and Variable Gain Amplifier (VGA). Gm-boost topology helps in increasing the gain while the current reuse technique provides less power consumption. Optimization algorithms simulated on MATLAB and the result shows minimum Noise Fig. (NF) is 2.62 dB, maximum gain is 17.8 dB, S11 i.e. input reflection coefficient is −13.5 dB and S22 i.e. output reflection coefficient is −14.7 dB at 50 Ω impedance matching while Figure of Merit1 (FoM1) is 36.14 dB using FA. The FA optimized parameters when simulated on Cadence Virtuoso software using GPDK 45 nm CMOS technology for the frequency range of 26–32 GHz then results show a minimum NF of 2.6 dB at 30.9 GHz, maximum gain of 16.9 dB at 30.5 GHz, S11 is −17.7 dB at 30.5 GHz, S22 is −21.2 dB at 29 GHz and FoM1 of 34.19 dB. The layout of the realized circuit has an area of 231.695 μm*164.48 μm i.e. 0.03811mm2.

A Low Noise Variable Gain Amplifier with 97.2 dB Linear Gain Range for CW Radar

This manuscript reports the design of a low noise variable gain amplifier (VGA) having wide dB linear gain characteristics for a continuous wave (CW) radar. A pseudo-exponential gain control function has been adopted in this VGA for the wide dB-linear behavior. Also, a BJT-based gain stage has been proposed to improve the gain dynamic range and low noise performance due to its higher transconductance/gain and lower flicker noise contribution. This proposed 2-gain stage VGA has been implemented in 130 nm SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) technology. This design performance has been benchmarked by post-layout simulation results. It has demonstrated a voltage-controlled gain from -33.6 dB to 74.4 dB (total 108 dB), with a 97.2 dB linear gain range, input referred noise of 2.4 nV /√Hz, and power consumption of 4.25 mW. This VGA has a 3-dB bandwidth of 10 MHz at a maximum gain of 74.4 dB and 251 MHz at a minimum gain of -33.6 dB with a chip layout area of 0.0682 mm2 . Compared to the latest available CMOS/BiCMOS VGAs in the literature, this proposed VGA has the highest gain dynamic range and dB-linear gain range with minimum input referred noise simultaneously across the operation bandwidth.

A 2.4 GHz Reconfigurable Cascode/Folded-Cascode Inductive Source Degenerated LNA With Enhanced OP1dB and OIP3 Over Gain Reduction

A 2.4 GHz reconfigurable cascode/folded-cascode inductive source degenerated LNA (ISDLNA) is proposed to implement the variable-gain functionality with enhanced output 1 dB compression point (OP1dB) and output third-order intercept point (OIP3) over the gain reduction, ensuring low noise figure (NF) of sub-1 dB at high gain mode. Depending on the channel condition, the LNA is designed to be operated as the cascode and folded-cascode ISDLNA through the digital switch control to have low NF of around 1 dB at high gain mode and high input P1dB (IP1dB) of greater than -5 dBm at low gain mode, respectively. To avoid the reliability issues caused by the overdriving control voltage of greater than the nominal supply voltage, the transmission gate switch is employed as the common gate stage of the cascode amplifier. In experiments, the proposed variable-gain LNA shows a power gain (S21), input return loss (S11), and NF of 11.8 dB, -31.8 dB, and 1.1 dB at high gain mode, and 5.0 dB, -14.4 dB, and 1.96 dB at low gain mode. In case of the linearity, the proposed LNA shows an IP1dB and input IP3 (IIP3) of -19.2 dBm and -5 dBm at high gain mode, and -5.1 dBm and +4.8 dBm at low gain mode, respectively. The power consumption for two operation modes is the same as 9.6 mW from a 1.2 V supply voltage.

A V‐band digitally controlled low noise variable gain amplifier with 3.5° phase variation in 28‐nm bulk CMOS

AbstractThis paper presents a V‐band digitally controlled low noise variable gain amplifier (LNVGA) in 28‐nm bulk CMOS process. The amplifier includes three stages and the first stage is used to realize wideband high gain and low noise figure (NF). The gain control is implemented in the second and third stages with current steering and split cascode topology, respectively. A source degeneration inductor and a series inductor are introduced to reduce the phase variation in the second stage. The phase response function is analyzed, and the phase reduction of 1.2° is achieved. Moreover, with the combination of these two different topologies, the phase variation can be further reduced. The measurement results show the LNVGA has a peak gain of 16 dB with a 3‐dB bandwidth of 45–59 GHz. The measured gain control range is 0–16 dB in 16 different gain states and the minimum phase variation is 3.5° with power consumption of 23 mW.

Design of 6 GHz Variable-Gain Low-Noise Amplifier Using Adaptive Bias Circuit for Radar Receiver Front End

This paper presents a variable-gain low-noise amplifier (VGLNA) based on an adaptive bias (ADB) circuit for the radar receiver front end. The ADB circuit processes the signal separated by a coupler at the LNA output port. First, the ADB circuit rectifies the coupled signal into positive DC voltage through a rectifier, which is then inverted to control a junction-gate field-effect transistor (JFET). The voltage-controlled current of JFET flows through a voltage-divider network and finally produces the DC biasing voltage for the BJT base termination, which decreases with the increase in the input RF power. The proposed VGLNA operates automatically in high gain at low input power and low gain at high input power, providing a wider dynamic range as compared to the constant-bias counterpart. For validation, a prototype is fabricated and measured at 6 GHz. As observed, the base biasing voltage generated by the ADB circuit is changed from 858 mV to 798 mV as the input power increases from −50 dBm to 0 dBm. As a result, the dynamic range represented by the input P1dB point (IP1dB) has an increase of 6.5 dB, while LNA still maintains a high gain of 15.15 dB at low input power.

A 5–6-GHz CMOS Beamforming Transceiver Front-End for Fiber-to-the-Room All-Optical Wi-Fi Solution

This letter presents a 5–6-GHz CMOS beamforming transceiver front-end with high linearity and low power consumption for fiber-to-the-room (FTTR) all-optical Wi-Fi solution, which can greatly reduce the transmission power and eliminate signal mutual interference among access points compared with traditional architecture, by aggregating beams of multichannel. The transmitter (TX) employs a high-linearity power amplifier, a variable-gain amplifier, a 5-bit passive attenuator (ATT), and a 4-bit passive phase shifter (PS). The receiver (RX) is composed of a single-to-differential variable gain low-noise amplifier (LNA), frequency-tuning buffers, a 5-bit ATT, and a 4-bit PS. Implemented in a 55-nm CMOS technology, the measured output power 1dB compression point (OP1dB) of TX is better than 12.1 dBm. The error vector magnitudes (EVMs) of the TX at 0-dBm output power with 80-MHz 256-quadrature amplitude modulation (QAM) orthogonal frequency division multiplexing (OFDM) signal are better than −36.3 dB, and the EVMs of the RX at −40 dBm input power are better than −37.8 dB. The noise figure is 4.3 dB in high-gain mode.

Integrated Hybrid Sub-Aperture Beamforming and Time-Division Multiplexing for Massive Readout in Ultrasound Imaging.

This paper demonstrates hybrid sub-aperture beamforming (SAB) with time-division multiplexing (TDM) for massive interconnect reduction in ultrasound imaging systems. A single-chip front-end system prototype has been fabricated in 180-nm HV BCD technology that combines 5×1 SAB with 8×1 TDM to efficiently reduce the number of receive signal interconnects by a factor of 40. The system includes on-chip high-voltage (HV) pulsers capable of generating unipolar pulses up to 70 V in transmit (TX) mode. The receiver (RX) chain consists of a T/R switch, a variable-gain low-noise amplifier (VG-LNA) with 4-step gain control (15-32 dB) for time-gain compensation followed by a programmable switched-capacitor analog delay-and-sum beamformer. The proof-of-concept prototype operates at a 200-MHz clock frequency and the SAB provides 32-step fine delays with a maximum delay of 310 ns corresponding to better than λ/20 delay quantization at 5 MHz. With these specifications, the SAB is capable of beam steering from 0 ° to 45 ° for a 5-element subarray with 150-micron pitch ( λ/2), providing a near-ideal phased array imaging performance. The sub-aperture beamformer is followed by the TDM system where each of the 8 channels is sampled at a rate of 25 MS/s after an anti-aliasing bandpass filter. The full functionality of the prototype chip is validated through electrical and acoustic measurements on a 1-D capacitive micromachined ultrasonic transducer (CMUT) array designed for intracardiac echocardiography (ICE).

A 20–42-GHz IQ Receiver in 22-nm CMOS FD-SOI With 2.7–4.2-dB NF and −25-dBm IP1dB for Wideband 5G Systems

This article presents a 20–42-GHz in-phase and quadrature (IQ) receiver in 22-nm CMOS fully depleted silicon on insulator (FD-SOI). The receiver includes a wideband low noise variable-gain amplifier (LN-VGA), double-balanced IQ mixers, wideband I/Q generation network and wideband local oscillator (LO) driver, low-pass filters, and wideband intermediate frequency (IF) amplifiers. The measured receiver has a peak conversion gain of 25.3 dB with a 3-dB bandwidth of 19.8–42 GHz and an I and Q bandwidth of 5.7 GHz and covers the 5G millimeter-wave (mm-wave) band. The measured single-sideband noise figure (NF) is 2.7–4.2 dB at 24–42 GHz with an IP1dB of −26 to −23 dBm. The I/Q downconverter consumes a total of 102 mW from 0.8- and 1.6-V supplies. The IP1dB can be improved by 5 dB with an NF degradation by only 1.2 dB using RF VGA gain control. At peak gain and −8-dB VGA setting, the receiver dynamic range is 64–68 dB for a 100-MHz bandwidth, which is very high for low power consumption. The gain and phase mismatch between the I and Q channels is < 0.6 dB and <6°, respectively. To the best of the authors’ knowledge, this is the first wideband I/Q receiver that covers the entire mm-wave 5G band based on GF 22-nm CMOS FD-SOI. The application area is multistandard multigigabit per second communication systems.

Design and performance analysis of low power LNA with variable gain current reuse technique

This paper presents a CMOS low power Variable Gain Low Noise Amplifier for 26–34 GHz in 45 nm process technology, which composes of cascaded complimentary common gate (CCG) stage and digital current steering amplifier. First stage is CCG stage, which helps in achieving the low power consumption and less area. Second stage is variable gain amplifier, uses current reuse technique as well as gm-boost technique and has constant dc current to make the input impedance stable. Source degeneration technique cancel out MOS parasitic capacitance help in achieving linearity. Simulated maximum peak gain is 13.139 dB at 30.57 GHz and lowest peak gain is 7.75 dB at 26 GHz i.e. approximately flat over the entire band. Lowest NF is 3.08 dB at 32.6 GHz. Process corner simulation has been done for all four corners (S–S, S–F, F–S, F–F) showing robustness of LNA. Input return loss has value less than − 9.58 dB while output return loss has less than − 2.6 dB showing good matching; power consumption is 16 mW for dc current of 16 mA at 1 V. MOS active chip area is 76.727 µm2.

A 17.5–23 GHz high precision phase shifting four‐channel satellite communication receiver with phase calibration technology

AbstractThis article presents a 130 nm SiGe BiCMOS four‐channel satellite communication receiver. Phased‐array system has become the optimal solution for satellite communication due to the electrical steering nature. In order to obtain wider bandwidth, higher precision of phase shift and smaller chip size, an improved quadrature network and a phase compensation technique are proposed in this article. Each channel consists of a cascade low noise variable gain amplifier with a high Q value inductor and an active vector synthetic phase shifter. The measurement results show that the receiver consumes only 193 mA current under 1.6 V supply voltage. The chip can achieve a gain of more than 23 dB (including synthesizer losses) from 19 to 23 GHz. From 17.5 to 23 GHz, the RMS phase shifting accuracy and attenuation accuracy are less than 2.7° and 1.1 dB, respectively. The noise figure and the gain variation are less than 2.3 dB and ± 1.5 dB, respectively. The total chip area is 3.5 × 1.8 mm2.

A DC to 220-GHz High-Isolation SPST Switch in 22-nm FDSOI CMOS

A wideband single-pole single-throw (SPST) switch covering the dc to 220-GHz frequency range is presented in this letter. A four-element distributed topology is used to extend operation to the upper millimeter-wave band. With a combination of front-gate and back-gate biasing, unique to fully depleted silicon-on-insulator (FDSOI) MOSFETs, and enabled by the thick metal/dielectric backend of the technology, the switch achieves an insertion loss of 3.1 dB and an isolation of 37 dB at 220 GHz, as well as a peak isolation of 58 dB at 200 GHz, without deembedding the pads. A G-band variable gain low-noise amplifier featuring the SPST switch shows >50-dB gain control range, with a maximum peak gain of 9.5 dB at 190 GHz and a 3-dB bandwidth from 180 to 203 GHz.

A K-Band Dual-Mode Common Gate Cross-Summing VG-LNA With Low Phase Variation

This brief presents a variable-gain low-noise amplifier (VG-LNA) with a common gate (CG) cross-summing configuration, which is fabricated using a 65-nm RF CMOS process. It has a wide gain control range as well as a high input 1 dB gain compression point (IP1dB) at high-gain by introducing a split common-gate transistor (SCGT) technique. In addition, output phase compensation is achieved by adopting a tuning capacitor at the cascode node. This LNA is designed as 2-stage cascode, and the area excluding the pad is 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It consumes 25.2 mW with a 1.2-V power supply. It shows a gain of 25 dB and a noise figure of 3.4 dB at 22 GHz. The measured minimum IP1dB is -27.5 dBm, and the root-mean-square phase error is 0.34° over the gain control range of 14 dB at 22 GHz.

A 6.5–12-GHz Balanced Variable-Gain Low-Noise Amplifier With Frequency-Selective Gain Equalization Technique

This article presents a wideband balanced variable-gain low-noise amplifier (VG-LNA) implemented in a 55-nm CMOS process. The proposed LNA has two cascode stages with an interstage matching transformer to constitute a fourth-order magnetically coupled resonator with two resonant peaks. The frequency-selective gain equalization technique is proposed to compensate for the gain variation of interstage dual-resonant tanks. This VG-LNA leverages a current-steering technique to realize a phase-invariant 18-dB tunable gain range with a measured input 1-dB gain compression point (IP1dB) at 9 GHz from -12.2 to -5 dBm. The LNA achieves a power gain of 20.2 dB with ±0.5-dB gain variation and a noise figure (NF) of 3.26 dB from 6.5 to 12 GHz. Due to the lumped Lange couplers, the input and output matching are both better than -14 dB. This chip occupies 1.44 × 0.68 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area excluding pads and consumes 75 mW.

An Ultra Low Cost Highly Reliable 18–22 GHz T/R Front-End With Adaptive Sensitivity, Rx Absorptive Calibration, and Fast Switching Time for Phased-Array Radars Applications

This letter proposes a fully integrated K-band front-end architecture for radars targeting extremely low NRE and RE. The RF front-end is composed of an SPDT-less half-duplex low-noise variable gain amplifier (LNVGA) co-designed with a power amplifier (PA) and an Rx coupler for A/ ${\varphi }$ calibration. The design architecture is built to answer to the multirange detection requirement of many phased-array applications and optimize their calibration in an array configuration. The half-duplex receiver has a gain ≥25 dB between 18 and 22 GHz and is integrating a current steering gain control mechanism for changing the Rx IP1dB up to −5 dBm. For this lowest sensitivity, the minimum 6.5-dB noise figure is affected by only 0.3 dB and conserves an AM-to-PM ≤2°. The half-duplex transmitter has a 34-dB small-signal gain and delivers at 20 GHz an output power of +18 dBm with a PAE of 16 % at 4-dB compression. The calibration circuit degrades the Rx noise figure by only 0.1-dB NF while acting as a coupler with 18-dB coupling and 21-dB directivity. The circuit with all its periphery can switch between Tx and Rx in less than 15 ns. Compared to the previous works in similar technology, performances were significantly improved. Despite the very low cost 180-nm CMOS process used, this SPDT-less T/R front-end architecture demonstrates excellent performances for radar applications at K-band frequencies, therefore, presenting a high performance-to-cost ratio. In terms of reliability, this circuit is designed for a life time of more than 106 h under HCI and TTBD degradations at continuous waves.

A 60 GHz Wideband, Low-Power Active Receiving Antenna With Adjustable Polarization for SNR Improvement

In this article, we propose a polarization adjustable active receiving antenna that covers the full 60 GHz ISM band (57–66 GHz) to improve the signal-to-noise ratio (SNR) degenerated by polarization mismatch with the transmitter. The proposed antenna not only controls the receiving angle of linear polarization (LP) but also controls the axial ratio of circular polarization (CP). For LP, the polarization angle is controlled from 0° to 180° in steps of 22.5°, while the axial ratio is controlled up to 2.6 dB by controlling the phase and amplitude of the phase shifter (P/S) and variable-gain low-noise amplifier (VGLNA) for CP case. The structure of the proposed antenna theoretically provides an SNR improvement of at least approximately 3 dB compared with the conventional active antenna in the worst case.

A $V$ -Band Low-Power Digital Variable-Gain Low-Noise Amplifier Using Current-Reused Technique With Stable Matching and Maintained OP1dB

This article presents a low-power CMOS digitally controlled variable gain low-noise amplifier (VGLNA) at $V$ -band in a 40-nm LP CMOS process. There are three amplifier stages and three digital gain control bits in this VGLNA. The first stage is a common source amplifier, and the second and third stages are current-reused amplifiers. In order to save dc power and control gain, we use the current-reused technique and add the digital switch between upper and lower transistors. Due to constant dc current, the input impedance of the current-reused stage is stable. Output impedance is stabilized by an ac grounding capacitor at the source terminal of the upper transistor under gain switching. Thus, our proposed VGA can minimize the interstage influence with the previous and following stage and maintain OP1dB due to the constant bias current. By adding a resonated inductor to cancel out the parasitic capacitance of switch transistor, we can keep bandwidth and improve noise figure (N.F.) at the current-reused stages under different gain states. The measured peak gain is 19.8 dB at 59.6 GHz, and lowest N.F. is 5.98 at 63.5 GHz. The gain states are 19.8/15.3/11.5/6.5 dB, respectively, and the measured input/output return loss is stable under different gain states. The IP1dB is increased from −29.5 to −17 dBm, and the OP1dB is nearly constant under different gain states. Total dc power consumption is only 18 mW for 1.1-V supplied voltage. This is the first digital current-reused VGLNA that has good FoM among digital VGLNA, the lowest dc power consumption, and compact die area at $V$ -band.

A 0.3–1.4 GHz inductorless CMOS variable gain LNA based on the inverter cell and self-forward-body-bias technique

In this paper, a low noise amplifier with variable gain is proposed in the frequency range of 0.3–1.4 GHz. The proposed circuit is composed of two inverter cell stages in which a variable feedback resistance is used to control the gain in the second stage. In both stages, self-forward-body-bias technique is utilized to reduce the power consumption and improve the circuit performance. High voltage gain, wide range of gain variation, low power consumption, and low noise figure are the most important features of the proposed variable gain low noise amplifier. The circuit is designed and simulated in standard 0.18-µm technology, and consumes 146 × 108 μm2 of chip area. Operated with a supply voltage of 1.2 V, power consumption of the proposed amplifier is 8 mW with a wide flat gain ranging from −24.9 to 21 dB in variable-gain mode of operation. The proposed circuit in the high-gain mode, operates as a low noise amplifier with high performance and low power consumption where the gain is greater than 20 dB, S11 is less than −24 dB, and noise figure is less than 2 dB in the entire operating frequency range. In this case, the IIP3 is equal to −9.5 dBm.

A Wideband Low-Noise Variable-Gain Amplifier With a 3.4 dB NF and up to 45 dB Gain Tuning Range in 130-nm CMOS

A 130 nm CMOS wideband (0.2 to 3.3 GHz) low-noise variable-gain amplifier (LNVGA) with two active baluns working for phase cancellation is presented herein. The LNVGA aims for a wide gain tuning range which avoids signal compression, while enabling a low noise figure. This figure is kept low by the first stage of the LNVGA, whereas the second stage provides the gain variation. The second stage is able to deliver a wide gain tuning range thanks to the utilization of the phase cancellation technique, which is implemented by two active baluns. Since the phase cancellation technique strongly relies on the balun output balancing, a low-imbalance active balun topology is being herein proposed, analyzed in detail, designed, and tested. This new LNVGA design achieves a gain tuning range of 45 dB, a noise figure of 3.4 dB, and dissipates 19 mW in the maximum gain condition. The circuit was fabricated in 130-nm CMOS with a 1.2-V supply.

A 17-to-24 GHz Low-Power Variable-Gain Low-Noise Amplifier in 65-nm CMOS for Phased-Array Receivers

This paper presents a low-power compact variable-gain low-noise amplifier that operates over the frequency band of 17–24 GHz. A design methodology is proposed to determine the optimal size of transistors to achieve the maximum possible gain for current-steering variable-gain amplifiers (VGAs). Moreover, the effect of gain switching on the input and output return losses of current-steering VGAs is analytically studied. Also, various structures of metal-oxide-metal capacitors are examined to find the optimal structure for high-frequency applications. A proof-of-concept VGA is fabricated in a 65-nm bulk CMOS process, and it is employed in a receiver chain. The designed VGA features about 13.3 dB maximum power gain with 5-bit resolution and an average noise figure of 3 dB. The achieved root-mean-square gain error is about 0.45 dB after the fabrication process. The output 1-dB compression point of the VGA is about − 1 dBm at the center of the frequency band. The VGA consumes about 4.2 mW from a 1-V supply, and excluding the pads, it occupies a silicon area of 0.23 mm2.

A 0.6-V Low-Power Variable-Gain LNA in 0.18-$\mu$ m CMOS Technology

A 0.6-V low-power variable-gain low-noise amplifier by using 0.18- ${\mu }\text{m}$ CMOS process has been proposed. By using a tunable negative-feedback capacitor technology, variable gain can be achieved. Moreover, forward body biasing, input feedback capacitor, current-reuse and multiple-gate topologies are utilized for realizing low power consumption, small chip area, and high linearity. The measured results show the power gain and input third-order intercept point ranges from 4 dB to 10 dB and 0 dBm, respectively at 2.8 GHz. The power consumption is 0.6 mW.