A 0.6-V Low-Power Variable-Gain LNA in 0.18-$\mu$ m CMOS Technology

Abstract

A 0.6-V low-power variable-gain low-noise amplifier by using 0.18- ${\mu }\text{m}$ CMOS process has been proposed. By using a tunable negative-feedback capacitor technology, variable gain can be achieved. Moreover, forward body biasing, input feedback capacitor, current-reuse and multiple-gate topologies are utilized for realizing low power consumption, small chip area, and high linearity. The measured results show the power gain and input third-order intercept point ranges from 4 dB to 10 dB and 0 dBm, respectively at 2.8 GHz. The power consumption is 0.6 mW.