Low-noise Programmable Gain Amplifier Research Articles

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

A low-noise programmable gain amplifier with fully balanced differential difference amplifier and class-AB output stage

A programmable gain amplifier (PGA) is presented, targeting amplifying input signal with high dynamic range and low noise. The proposed PGA adopts fully balanced differential difference amplifier (FBDDA) as main amplifier. A class-AB implementation of output stage is advantageous in order to achieve high current driving capability with very low quiescent power consumption. Combining resistor-feedback loop controlled by digital signal, the proposed PGA achieves a dB-linear gain range from 0 to 15dB with a gain step of 1dB. Compared with previous works, the theoretical analysis and measurement results prove that the proposed structure has lower noise. The circuit was designed and fabricated in SMIC 0.18µm 3.3V process, showing a gain error of less than 0.25dB, a third harmonic distortion (HD3) of better than −83dB and a thermal noise of 1.6 nv/Hz. The measurement results indicate that the PGA described here has a −3dB bandwidth of 387.5MHz at maximum gain of 15dB. The PGA occupies a chip area of 0.1mm2.