Low Noise Charge Sensitive Amplifier Research Articles

GRAPH — an readout ASIC for large MCP based detectors

We present a programmable 16 channel, mixed signal, low power readout ASIC, having the project historically named Gigasample Recorder of Analog waveforms from a PHotodetector (GRAPH). It is designed to read large aperture single photon imaging detectors using micro channel plates for charge multiplication, and measuring the detector's response on crossed strips anodes to extrapolate the incoming photon position. Each channel consists of a fast, low power and low noise charge sensitive amplifier, which provides a myriad of coarse and fine programmable options for gain and shaping settings. Further, the amplified signal is recorded using, to our knowledge novel, the Hybrid Universal sampLing Architecture (HULA) ADC. A kind of mixed signal double buffer memory, that enables concurrent waveform recording, and selected event digitized data extraction. The sampling frequency is freely adjustable between few kHz up to 125 MHz, while the chip's internal digital memory holds a history 2048 samples for each channel, with a digital headroom of 12 bits. An optimized region of interest sample-read algorithm allows to extract the information just around the event pulse peak, while selecting the next event, thus substantially reducing the operational dead time. The chip is designed in 130 nm TSMC CMOS technology, and its power consumption is around 47 mW per channel.

A Time-over-Threshold asynchronous front-end in 28 nm CMOS for the readout of pixel detectors in extreme radiation environments

This work describes the design, in a 28 nm CMOS technology, of a front-end channel for the readout of pixel sensors in future particle accelerators. The channel being developed leverages the Time-Over-Threshold technique for the numerical conversion of the detector signal amplitude, and includes a low-noise charge sensitive amplifier featuring a compact gain stage architecture. The front-end circuit features an equivalent noise charge not exceeding 70 electrons r.m.s. for a detector capacitance of 50 fF, with a threshold dispersion of the order of 20 electrons r.m.s. A prototype chip including a matrix of 8x32 readout channels has been submitted for fabrication. The design of the front-end channel, together with the main simulation results, is discussed in the paper.

Design and Characterization of a Low-Noise and Low-Background Charge Sensitive Amplifier for the Readout of Germanium Detectors

Design and Characterization of a Low-Noise and Low-Background Charge Sensitive Amplifier for the Readout of Germanium Detectors

A novel silicon pixel sensor for beam monitoring applications at heavy-ion accelerators

This paper describes a silicon pixel sensor for non-interceptive real-time beam monitoring at heavy-ion accelerators. The total size of the sensor is 4 mm × 5 mm. It has 64 (row) × 120 (column) square pixels, each single of which is in the size of 40 μm × 40 μm. With the exposed sensing pad, this sensor can directly collect the charge in the media over the pixels. The in-pixel circuit mainly consists of a low-noise Charge Sensitive Amplifier (CSA) to establish the signal for the energy reconstruction and a discriminator with a Time-to-Amplitude Converter (TAC) for the Time of Arrival (TOA) measurement. The analog signal from each pixel is accessible through time-shared multiplexing over the entire pixel array. This paper will discuss the design of this IMPix-S1 sensor.

Advances in High-Energy-Resolution CdZnTe Linear Array Pixel Detectors with Fast and Low Noise Readout Electronics.

Radiation detectors based on Cadmium Zinc Telluride (CZT) compounds are becoming popular solutions thanks to their high detection efficiency, room temperature operation, and to their reliability in compact detection systems for medical, astrophysical, or industrial applications. However, despite a huge effort to improve the technological process, CZT detectors' full potential has not been completely exploited when both high spatial and energy resolution are required by the application, especially at low energies (<10 keV), limiting their application in energy-resolved photon counting (ERPC) systems. This gap can also be attributed to the lack of dedicated front-end electronics which can bring out the best in terms of detector spectroscopic performances. In this work, we present the latest results achieved in terms of energy resolution using SIRIO, a fast low-noise charge sensitive amplifier, and a linear-array pixel detector, based on boron oxide encapsulated vertical Bridgman-grown B-VB CZT crystals. The detector features a 0.25-mm pitch, a 1-mm thickness and is operated at a -700-V bias voltage. An equivalent noise charge of 39.2 el. r.m.s. (corresponding to 412 eV FWHM) was measured on the test pulser at 32 ns peaking time, leading to a raw resolution of 1.3% (782 eV FWHM) on the 59 keV line at room temperature (+20 °C) using an uncollimated 241Am, largely improving the current state of the art for CZT-based detection systems at such short peaking times, and achieving an optimum resolution of 0.97% (576 eV FWHM) at 1 µs peaking time. The measured energy resolution at the 122 keV line and with 1 µs peaking time of a 57Co raw uncollimated spectrum is 0.96% (1.17 keV). These activities are in the framework of an Italian collaboration on the development of energy-resolved X-ray scanners for material recycling, medical applications, and non-destructive testing in the food industry.

A low-power analog front-end amplifier for SiPM based radiation detectors

A low-power analog front-end amplifier for SiPM based radiation detectors is presented. In particular, an event-driven low-noise charge sensitive amplifier (CSA) is developed in conjunction with a novel charge division scheme by capacitively coupling the SiPM to the CSA so that the SiPM’s linear energy-charge correlation is preserved, while conserving power. Following extensive circuit simulations and design finalization, a test chip containing the presented front-end amplifier has been fabricated in the target 65 nm CMOS technology. The fabricated prototype and the presented SiPM read-out approach have been verified and characterized using a dedicated test setup. An energy resolution of 11.7% is achieved for the 511 keV peak of a Na-22 source and 10.9% for the 662 keV peak of a Cs-137 source, using an onsemi 3 mm × 3 mm SiPM and a LYSO scintillator coupled to the fabricated CSA. The front-end amplifier consumes 350 μW of power, while maintaining linearity across a wide energy range following calibration. Including the active amplifier circuitry, the bias generator section, and the capacitor bank that realizes the feedback capacitor Cfb of the CSA, the front-end amplifier occupies a silicon area of 50,000 μm2, which supports low-power, multi-channel read-out realizations within a small footprint.

An efficient design of 45-nm CMOS low-noise charge sensitive amplifier for wireless receivers

&lt;p&gt;Amplifiers are widely used in signal receiving circuits, such as antennas, medical imaging, wireless devices and many other applications. However, one of the most challenging problems when building an amplifier circuit is the noise, since it affects the quality of the intended received signal in most wireless applications. Therefore, a preamplifier is usually placed close to the main sensor to reduce the effects of interferences and to amplify the received signal without degrading the signal-to-noise ratio. Although different designs have been optimized and tested in the literature, all of them are using larger than 100 nm technologies which have led to a modest performance in terms of equivalent noise charge (ENC), gain, power consumption, and response time. In contrast, we consider in this paper a new amplifier design technology trend and move towards sub 100 nm to enhance its performance. In this work, we use a pre-well-known design of a preamplifier circuit and rebuild it using 45 nm CMOS technology, which is made for the first time in such circuits. Performance evaluation shows that our proposed scaling technology, compared with other scaling technology, extremely reduces ENC of the circuit by more than 95%. The noise spectral density and time resolution are also reduced by 25% and 95% respectively. In addition, power consumption is decreased due to the reduced channel length by 90%. As a result, all of those enhancements make our proposed circuit more suitable for medical and wireless devices.&lt;/p&gt;

Slice-Based Analog Design

Advances over the last decades in electronic design automation (EDA) for the design of digital integrated circuits (ICs), have led to the development of a robust set of tools and methodologies that automate almost all low-level phases of the digital design workflow. In contrast, analog IC design remains a mostly handmade, time-consuming and knowledge-intensive process. The amount of design iterations can be heavily cut down by the use of realistic value tables through the $g_{m}/I_{D}$ design technique; however, the process still remains time-consuming and error-prone, with an end result of limited applicability beyond the scope of the initial specifications. The slice-based design methodology, first introduced in this paper, is a new approach to analog IC design, suitable for implementation in EDA tools, that aims to reduce the amount of time and expertise required from the user. This methodology, inspired by the $g_{m}/I_{D}$ design technique, is based on the use of pre-designed circuit cells, which can be connected in parallel to scale important performance metrics. Although not limited to any particular fabrication process, the present paper explores the application of the proposed design methodology to CMOS technologies, and in the context of a particular target application: low-noise charge-sensitive amplifiers (CSA) used for instrumentation in particle physics experiments. The methodology was successfully applied and validated through the design, fabrication and testing of a CSA with configurable noise performance.

Research on High-Resolution Miniaturized MEMS Accelerometer Interface ASIC.

High-precision microelectromechanical system (MEMS) accelerometers have wide application in the military and civil fields. The closed-loop microaccelerometer interface circuit with switched capacitor topology has a high signal-to-noise ratio, wide bandwidth, good linearity, and easy implementation in complementary metal oxide semiconductor (CMOS) process. Aiming at the urgent need for high-precision MEMS accelerometers in geophones, we carried out relevant research on high-performance closed-loop application specific integrated circuit (ASIC) chips. According to the characteristics of the performance parameters and output signal of MEMS accelerometers used in geophones, a high-precision closed-loop interface ASIC chip based on electrostatic time-multiplexing feedback technology and proportion integration differentiation (PID) feedback control technology was designed and implemented. The interface circuit consisted of a low-noise charge-sensitive amplifier (CSA), a sampling and holding circuit, and a PID feedback circuit. We analyzed and optimized the noise characteristics of the interface circuit and used a capacitance compensation array method to eliminate misalignment of the sensitive element. The correlated double sampling (CDS) technology was used to eliminate low-frequency noise and offset of the interface circuit. The layout design and engineering batch chip were fabricated by a standard 0.35 μm CMOS process. The active area of the chip was 3.2 mm × 3 mm. We tested the performance of the accelerometer system with the following conditions: power dissipation of 7.7 mW with a 5 V power supply and noise density less than 0.5 μg/Hz1/2. The accelerometers had a sensitivity of 1.2 V/g and an input range of ±1.2 g. The nonlinearity was 0.15%, and the bias instability was about 50 μg.

Topmetal-M: A novel pixel sensor for compact tracking applications

The Topmetal-M is a large area pixel sensor (18 mm × 23 mm) prototype fabricated in a new 130 nm high-resistivity CMOS process in 2019. It contains 400 rows × 512 columns square pixels with the pitch of 40μm. In Topmetal-M, a novel charge collection method combining the Monolithic Active Pixel Sensor (MAPS) and the Topmetal sensor has been proposed for the first time. Both the ionized charge deposited by the particle in the sensor and along the track over the sensor can be collected. The in-pixel circuit mainly consists of a low-noise charge sensitive amplifier to establish the signal for the energy reconstruction, and a discriminator with a Time-to-Amplitude Converter (TAC) for the Time of Arrival (TOA) measurement. With this mechanism, the trajectory, particle hit position, energy, and arrival time of the particle can be measured. The analog signal from each pixel is accessible through time-shared multiplexing over the entire pixel array. This paper will discuss the design and preliminary test results of the Topmetal-M sensor.

A 64-channel integrated circuit for signal readout from coordinate detectors

A specialized integrated circuit was developed for the readout of signal from coordinate detectors of different types, including gas micro-pattern detectors and silicon microstrip detectors. The ASIC includes 64 channels, each containing a low-noise charge-sensitive amplifier with a connectable feedback capacitor and resistor, and fast reset of the feedback capacitor. Each channel of the ASIC also contains 100 cells of analogue memory where the signal can be stored at a rate of 10 MHz. The pitch of input pads is 50 μm and the chip size is 5× 5 mm2. The equivalent noise charge of the ASIC channel is about 2000 electrons with 10 pF capacitance at the input and maximal signal before saturation corresponds to 2× 106 electrons. The first application for this ASIC is the detector for imaging of explosions at a synchrotron radiation beam (DIMEX), where it has to substitute the old and slower APC128 ASIC. The full-size electronics including 8 ASICs for 512 channels was assembled and tested.

A fast, low power and low noise charge sensitive amplifier ASIC for a UV imaging single photon detector

NASA has funded, through their Strategic Astrophysics Technology (SAT) program, the development of a cross strip (XS) microchannel plate (MCP) detector with the intention to increase its technology readiness level (TRL), enabling prototyping for future NASA missions. One aspect of the development is to convert the large and high powered laboratory Parallel Cross Strip (PXS) readout electronics into application specific integrated circuits (ASICs) to decrease their mass, volume, and power consumption (all limited resources in space) and to make them more robust to the environments of rocket launch and space. The redesign also foresees to increase the overall readout event rate, and decrease the noise contribution of the readout system. This work presents the design and verification of the first stage for the new readout system, the 16 channel charge sensitive amplifier ASIC, called the CSAv3. The single channel amplifier is composed of a charge sensitive amplifier (pre-amplifier), a pole zero cancellation circuit and a shaping amplifier. An additional output stage buffer allows polarity selection of the output analog signal. The operation of the amplifier is programmable via serial bus. It provides an equivalent noise charge (ENC) of around 600 e^− and a baseline gain of 10 mV/fC. The full scale pulse shaped output signal is confined within 100 ns, without long recovery tails, enabling up to 10 MHz periodic event rates without signal pile up. This ASIC was designed and fabricated in 130 nm, TSMC CMOS 1.2 V technology. In addition, we briefly discuss the construction of the readout system and plans for the future work.

PFM2: a 32 × 32 processor for X-ray diffraction imaging at FELs

This work is concerned with the design of a readout chip for application to experiments at the next generation X-ray Free Electron Lasers (FEL). The ASIC, named PixFEL Matrix (PFM2), has been designed in a 65 nm CMOS technology and consists of 32 × 32 pixels. Each cell covers an area of 110 × 110 μm2 and includes a low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time-variant shaper used to process the preamplifier output signal, a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC) and digital circuitry for channel control and data readout. Two different solutions for the readout channel, based on different versions of the time-variant filter, have been integrated in the chip. Both solutions can be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future X-ray FEL machines. The ASIC will be bump bonded to a slim/active edge pixel sensor to form the first demonstrator for the PixFEL X-ray imager. This work has been carried out in the frame of the PixFEL project funded by Istituto Nazionale di Fisica Nucleare (INFN), Italy.

Dynamic Compression of the Signal in a Charge Sensitive Amplifier: From Concept to Design

This work is concerned with the design of a low-noise Charge Sensitive Amplifier featuring a dynamic signal compression based on the non-linear features of an inversion-mode MOS capacitor. These features make the device suitable for applications where a non-linear characteristic of the front-end is required, such as in imaging instrumentation for free electron laser experiments. The aim of the paper is to discuss a methodology for the proper design of the feedback network enabling the dynamic signal compression. Starting from this compression solution, the design of a low-noise Charge Sensitive Amplifier is also discussed. The study has been carried out by referring to a 65 nm CMOS technology.

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

Note: A charge sensitive spectroscopy amplifier for position sensitive micro-channel plate detectors.

A compact and low noise charge sensitive spectroscopy amplifier which can be integrated into position sensitive micro-channel plate (MCP) detectors has been constructed. The amplifier was optimized by using a wave form generator and tested by a chevron shape MCP detector. The output noise of 4 mV(rms) was achieved while the gain is 10(12) V/C and the shaping time is 700 ns.

CALORIC: A Readout Chip for High Granularity Calorimeter

A very-front-end electronics has been developed to fulfil requirements for the next generation of electromagnetic calorimeters. The compactness of this kind of detector and its large number of channels (up to several millions) impose a drastic limitation of the power consumption and a high level of integration. The electronic channel proposed is first of all composed of a low-noise Charge Sensitive Amplifier (CSA) able to amplify the charge delivered by a silicon diode up to 10pC. Next, a two-gain shaping, based on a Gated Integration (G.I.), is implemented to cover the 15 bits dynamic range required: a high gain shaper processes signals from 4 fC (charge corresponding to the MIP) up to 1pC, and a low gain filter handles charges up to 10 pC. The G.I. performs also the analog memorization of the signal until it is digitalized. Hence, the analog-to-digital conversion is carried out through a low-power 12-bit cyclic ADC. If the signal overloads the high-gain channel dynamic range, a comparator selects the low-gain channel instead. Moreover, an auto-trigger channel has been implemented in order to select and store a valid event over the noise. The timing sequence of the channel is managed by a digital IP. It controls the G.I. switches, generates all needed clocks, drives the ADC and delivers the final result over 12 bits. The whole readout channel is power controlled, which permits to reduce the consumption according to the duty cycle of the beam collider. Simulations have been performed with Spectre simulator on the prototype chip designed with the 0.35μm CMOS technology from Austriamicrosystems. Results show a non-linearity better than 0.1% for the high-gain channel, and a non-linearity limited to 1% for the low-gain channel. The Equivalent Noise Charge referred to the input of the channel is evaluated to 0.4 fC complying with the MIP/10 limit. With the timing sequence of the International Linear Collider, which presents a duty cycle of 1%, the power consumption of the complete channel is limited to 43 μW thanks to the power pulsing. The total area of the channel is 1.2 mm2 with an analog memory depth of 16.

Signal Processing for High Granularity Calorimeter: Amplification, Filtering, Memorization, and Digitalization

A dedicated very-front-end (VFE) readout channel for high-granularity calorimeters has been designed, fabricated and evaluated. This electronics is composed of a low-noise charge-sensitive amplifier followed by a bandpass filter based on a gated integrator. The efficiency of the gated integrator, a time-variant filter, in terms of noise rejection has been compared to an equivalent time-invariant filter, a CRRC shaper. Their serial and parallel noise indexes have been evaluated by simulation for different values of integration and peaking times. Results show that the gated integrator is a more efficient filter than the CRRC shaper, thanks to the time of integration which can be expanded to approach the time interval between two successive bunch crossings, whereas the peaking time of the CRRC shaper is limited by pile-up considerations. Moreover, the gated integrator intrinsically includes the capacitor required to perform the analog memorization of the signal before its delayed digital conversion. This analog-to-digital conversion is carried out by a 12-bit cyclic ADC specifically developed for this application. The very-front-end channel has been evaluated using a 0.35 μm CMOS technology. Measurements show a global non-linearity better than 0.1%. The Equivalent Noise Charge at the input of the channel is evaluated to 1.8 fC, to be compared to the maximum input charge of 10 pC. The power consumption of the complete channel is limited to 6.5 mW.

Development of a Low-Noise Front-End Readout Chip Integrated With a High-Resolution TDC for APD-Based Small-Animal PET

This paper presents the design of a low-noise multi-channel front-end readout chip integrated with a high-resolution TDC. It is foreseen to be used as front-end readout electronics of Avalanche Photo Diodes (APD) dedicated to a small animal Positron Emission Tomography (PET) system. The architecture of the chip is reported. Two prototype chips, a ten-channel front-end chip and a three-channel high-resolution TDC, have been designed in AMS 0.35 μm CMOS technology. A low-noise charge-sensitive amplifier (CSA) and a shaper are integrated in each channel of the front-end chip. The proposed CSA performs a compensation of the 40 nA dark current coming from the detector. An equivalent input noise charge of 275 e- + 10 e-/pF (rms) has been obtained from test. The TDC chip is based on coarse-fine two-level conversion scheme. In the coarse conversion, a 10-bit counter is employed to achieve a wide range. Meanwhile, the time interpolation using an array of delay-locked loops is proposed for fine conversion. The measured time range is 10 μs. The bin size has been achieved from 71 ps to 142 ps with a reference clock from 100 MHz to 50 MHz.

Signal processing for high granularity calorimeter: amplification, filtering, memorization and digitalization

A very-front-end electronics dedicated to high granularity calorimeters has been designed and its performance measured. This electronics performs the amplification of the charge delivered by the detector thanks to a low-noise Charge Sensitive Amplifier. The dynamic range is improved using a bandpass filter based on a Gated Integrator. Studying its weighting function, we show that this filter is more efficient than standard CRRC shaper, thanks to the integration time which can be expand near the bunch interval time, whereas the peaking time of the CRRC shaper is limited to pile-up consideration. Moreover, the Gated Integrator performs intrinsically the analog memorization of the signal before its delayed digital conversion. The analog-to-digital conversion is performed through a 12-bit cyclic ADC specifically developed for this application.The very-front-end channel has been fabricated using a 0.35 μm CMOS technology. Measurements show a global non-linearity better than 0.1%. The Equivalent Noise Charge at the input of the channel is evaluated to 1.8 fC, compare to the maximum input charge of 10 pC. The power consumption of the complete channel is limited to 6.5 mW.