Low-noise Architecture Research Articles

An electrochemical sensor for monitoring biogenic amines in anchovies as quality and safety index

In this paper an electrochemical sensor for the monitoring of anchovy’s shelf life is presented. The device has been developed addressing three user needs critical in food application: fast response, high reproducibility and ease of use. The system is composed of an electronic interface optimized with a low noise architecture coupled with a non-functionalized commercial screen printed electrode (SPE). The stability of the measuring process is ensured by the electronic feedback, and the interactions with the solutions are not mediated by a sensing material. The sensor has been calibrated against different concentration levels of seven specific biogenic amines (BAs) associated with the degradation of anchovies: β-phenylethylamine (β-PEA), putrescine (PUT), cadaverine (CAD), histamine (HIS), tyramine (TYR), spermine (SPM) and spermidine (SPD). This proof-of-concept experiment evidenced the potentialities of this technology both in BAs quantification and in monitoring anchovy’s spoilage. The results obtained have been compared with LC-UV as standard laboratory instrument. After a first calibration step with standard BAs, the sensor has been tested in the monitoring of anchovy’s samples stored for ten days at a temperature of 2 ± 1 °C. Sensors’ responses followed samples evolution against time in accordance with LC-UV results. Further developments are requested to set up a standard method for the industrial application of the sensor, but rapidity, low-cost and the ease of use account for its relevance as device to be used on field.

Electrodes for Beam Position Monitors for Fourth Generation Synchrotron Radiation Source

Fourth-generation synchrotron radiation sources demand new quality for the electron beam diagnostic systems. Some of diagnostic system elements have to be accurately developed or redeveloped due to match the new requirements. Beam position monitor (BPM) is a most used detector and tens (even hundreds) BPMs are installed in numerous positions along beam transfer lines, booster and storage rings. Modern approach to this device development assumes such features as short transient time, wide bandwidth, high sampling rate, low noise architecture and reasonable production and maintenance price. As a part of the system, the BPM electrodes should meet all those requirements. In this article we describe a development procedure for high quality capacitive electrodes for the BPM. 3D electromagnetic model allows estimation of the sensitivity, frequency response and tolerance requirements for the manufacturing of hundreds of monitors. Presented here equivalent scheme for the electrodes is a basis for the BPM electronics design.

A Study on Advanced High Speed and Ultra Low Power ADC Architectures

Background: Analog-to-digital converter (acronym as ADC) is an electronics device used to convert a continuous physical signal to a digital number. Over recent years, different advancement has been done and both the beginner as well as expert can be bewildered to differentiate their limitations and benefits. Objective: To overcome this problem this paper provides a brief study about these advance architectures and their parameters. The deliberation of these parameters can make a suitable decision to adopt a better architecture for the purpose of research. Methods: reviewed in this paper include parametric and non parametric ultra low, high speed, low noise architectures.

Scalable, Low-Noise Architecture for Integrated Terahertz Imagers

We propose a scalable, low-noise imager architecture for terahertz recordings that helps to build large-scale integrated arrays from any field-effect transistor (FET)- or HEMT-based terahertz detector. It enhances the signal-to-noise ratio (SNR) by inherently enabling complex sampling schemes. The distinguishing feature of the architecture is the serially connected detectors with electronically controllable photoresponse. We show that this architecture facilitate room temperature imaging by decreasing the low-noise amplifier (LNA) noise to one-sixteenth of a non-serial sensor while also reducing the number of multiplexed signals in the same proportion. The serially coupled architecture can be combined with the existing read-out circuit organizations to create high-resolution, coarse-grain sensor arrays. Besides, it adds the capability to suppress overall noise with increasing array size. The theoretical considerations are proven on a 4 by 4 detector array manufactured on 180 nm feature sized standard CMOS technology. The detector array is integrated with a low-noise AC-coupled amplifier of 40 dB gain and has a resonant peak at 460 GHz with 200 kV/W overall sensitivity.

EMC Optimized Design of Linear Regulators Including a Charge Pump

The charge pump belongs to the most critical blocks for electromagnetic compatibility (EMC) of low dropout linear regulators (LDO) because of its switching nature. The goal of this paper is to contribute charge pump design practice and a prediction method for the LDO EMC performance already in an early design phase. LDO noise coupling mechanisms are analyzed. EMC aware circuit design includes the choice of low-noise architectures, the right switching frequency, and noise filtering. The derived simulation method shows very good matching with EMC test results for an LDO with two different charge pumps fabricated in 350 nm high-voltage BiCMOS technology. For a realistic prediction of the EMC noise magnitude, a relative simple simulation setup gives results with less than 3 dB μV accuracy. A tripler current mode charge pump turned out to be well suitable for EMC. Conducted emissions could be predicted and confirmed to be improved by ~50 dBμV versus a conventional voltage-mode charge pump.

Area-Efficient Low-Noise Low-Spur Architecture for an Analog PLL Working From a Low Frequency Reference

This brief presents an area-efficient low-noise architecture for an analog phase-locked loop (PLL) working off a low frequency reference. The architecture has been demonstrated in a 100-400-MHz PLL implemented for wireless connectivity and broadcast applications. It can easily be extended to gigahertz (GHz) operations. A low reference frequency forces a low loop bandwidth, which requires large loop filter components. The challenge is to keep the area small while meeting the jitter specs. By using a charge-pumpless architecture with a novel windowing function, we were able to stabilize the loop with a large resistor and a moderate capacitor without degrading phase noise due to the large thermal noise from the resistor. This provides substantial advantage for area reduction. The windowing function also improves leakage-induced spurs by 16 dB. The PLL was designed in a 45-nm CMOS all-digital process. It occupies an area of 0.09 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and draws a total current of 800 μA.