Low Noise Amplifier Research Articles

Nanosecond pulsed current source for light emitting diode (LED) driven photoacoustic signal acquisition systems

Abstract Photoacoustic imaging (PAI) is gaining attention for its non-invasive diagnostic capabilities. Traditionally, bulky and expensive laser systems have been used as excitation light sources in PAI, posing challenges for translation and remote applications. High-power light emitting diodes (LEDs) can be an alternative light source. However, the necessary driver circuitry has not been extensively studied for driving the nanoseconds pulsed LEDs. This study develops and demonstrate for the first time the full circuit, performance, optimization and operating procedures of a nanosecond pulsed current source (NSPCS) to drive a high-power, high-speed LED array for PAI. The NSPCS driver can deliver tunable pulsed LED currents between 0 and 20 A, pulse widths of 50–100 ns, and trigger pulse repetition rates up to 20 kHz, achieving a driver efficiency of 58.27%. It can drive an array of 37 high-power LEDs (850 nm wavelength) with an electrical-to-optical efficiency of 24.8%. Illumination with this LED array produced a photoacoustic signal (after 79 dB amplification with low-noise amplifier) of 3.92 V (peak-to-peak) and a signal-to-noise ratio of 79.36 dB. The NSPCS circuit has demonstrated effective generation of tunable high-current pulses for LED-based PAI applications.

A 13–33 GHz Wideband Low-Noise Amplifier in 150-nm GaAs Based on Simultaneous Noise- and Input-Matched Gain-Core with R-L-C Shunt Feedback Network

This work reports the concept of a shunt negative feedback technique for implementing a millimeter-wave wideband low-noise amplifier. The proposed shunt negative feedback network consists of a resistor–capacitor–inductor configuration. The proposed feedback network can achieve simultaneous noise and input matching (SNIM) over a wide frequency range by adjusting the values of the resistor–capacitor–inductor configuration based on numerical analysis. By adopting the SNIM-based gain core as the first stage of the amplifier, the simulation results of the three-stage low-noise amplifier in a 150-nm GaAs pHEMT process achieve a gain of 15.6–18.6 dB and a noise figure of 1.05–2.8 dB in the frequency range of 13–33 GHz, respectively, while dissipating 99 mW.

Low-noise microwave parametric amplifier based on self-heated nonlinear impedance with subnanosecond thermal response

Low-noise microwave parametric amplifier based on self-heated nonlinear impedance with subnanosecond thermal response

Design of Interface ASIC with Power-Saving Switches for Capacitive Accelerometers.

High-precision, low-power MEMS accelerometers are extensively utilized across civilian applications. Closed-loop accelerometers employing switched-capacitor (SC) circuit topologies offer notable advantages, including low power consumption, high signal-to-noise ratio (SNR), and excellent linearity. Addressing the critical demand for high-precision, low-power MEMS accelerometers in modern geophones, this work focuses on the design and implementation of closed-loop interface ASICs (Application-Specific Integrated Circuits). The proposed interface circuit, based on switched-capacitor modulation technology, incorporates a low-noise charge amplifier, sample-and-hold circuit, integrator, and clock divider circuit. To minimize average power consumption, a switched operational amplifier (op-amp) technique is adopted, which temporarily disconnects idle op-amps from the power supply. Additionally, a class-AB output stage is employed to enhance the dynamic range of the circuit. The design was realized using a standard 0.35 μm CMOS process, culminating in the completion of layout design and small-scale engineering fabrication. The performance of the MEMS accelerometers was evaluated under a 3.3 V power supply, achieving a power consumption of 3.3 mW, an accelerometer noise density below 1 μg/√Hz, a sensitivity of 1.65 V/g, a measurement range of ±1 g, a nonlinearity of 0.15%, a bandwidth of 300 Hz, and a bias stability of approximately 36 μg. These results demonstrate the efficacy of the proposed design in meeting the stringent requirements of high-precision MEMS accelerometer applications.

Simulation of high signal-to-noise ratio resonant photodetector for homodyne measurement and its verification.

In this paper, two models for simulating the shot noise and electronic noise performances of resonant photodetectors designed for homodyne measurements are presented. One is based on a combination of a buffer and a low-noise amplifier, and the other is based on an operational amplifier. Through the comparisons between the numerical simulation results and the experimentally obtained data, excellent agreements are achieved, which show that the models provide a highly efficient guide for the development of a high signal-to-noise ratio (SNR) resonant photodetector. Furthermore, we demonstrate a high SNR resonant photodetector for homodyne measurements at the 147MHz optical sideband, achieving a 20.8 dB SNR of the shot noise to the electronic noise with a 2 mW optical signal input, utilizing a combination of a buffer and a low-noise amplifier. Concurrently, we have obtained another resonant photodetector at the 1.14GHz optical sideband, which exhibits a 13 dB SNR based on an operational amplifier.

An Automated Circuit Topology Generation and Optimization Method for CMOS Low-Noise Amplifiers

An Automated Circuit Topology Generation and Optimization Method for CMOS Low-Noise Amplifiers

A 0.73 dB Multi-Gain Low Noise Amplifier Design with Fast Mode-Switching for 5G/4G Applications.

In this paper, a sub-1dB Low Noise Amplifier (LNA) with several gain modes, including amplification and attenuation modes required for the fifth and fourth generations (5G/4G) of mobile network applications, is proposed. Its current consumption is adaptive for every gain mode and varies to lower currents for lower amplifications due to the importance of current consumption for mobile network applications. The proposed LNA features an innovative architecture with a three-core input structure supporting multi-gain modes, achieving high gain and ultra-low noise performance. Additionally, the design integrates a cascade switching mechanism to ensure fast transitions between the gain modes and maintain operational stability. A reconfigurable input structure is introduced to support multiple input stages, enabling the proposed LNA to be compatible with both 5G and 4G applications. The proposed design demonstrates the implementation of seven distinct gain modes with a maximum current consumption of 11.68 mA, achieving proper input matching in each gain mode. The LNA delivers a maximum gain of 20.4 dB with a noise figure of 0.73 dB. Moreover, the most stringent mode switching condition achieved, the ON time, is as short as 1.295 µs, and the gain mode transition speed is an impressive 0.874 µs, ensuring extremely fast mode transitions. The proposed LNA occupies an area of 700 µm × 500 µm and is fabricated using a 65 nm FD-SOI process.

Room-Temperature Solid-State Maser Amplifier

Masers once represented the state of the art in low-noise microwave amplification technology but eventually became obsolete due to their need for cryogenic cooling. Masers based on solid-state spin systems perform most effectively as amplifiers, since they provide a large density of spins and can, therefore, operate at relatively high powers. While solid-state maser oscillators have been demonstrated at room temperature, continuous-wave amplification in these systems has only ever been realized at cryogenic temperatures. Here, we report on a continuous-wave solid-state maser amplifier operating at room temperature. We achieve this feat using a practical setup that includes an ensemble of nitrogen-vacancy center spins in a diamond crystal, a strong permanent magnet, and a simple laser diode. We describe important amplifier characteristics including gain, bandwidth, compression power, and noise temperature and discuss the prospects of realizing a room-temperature near-quantum-noise-limited amplifier with this system. Finally, we show that in a different mode of operation the spins can be used to reduce the microwave noise in an external circuit to cryogenic levels, all without the requirement for physical cooling. Published by the American Physical Society 2024

An ultra-wideband current-reused LNA MMIC with negative feedback and adaptive bias networks

Abstract An ultra-wideband current-reused low-noise amplifier (LNA) monolithic microwave integrated circuit design is presented in this letter. Negative feedback networks are employed at both stages of the proposed LNA to expand bandwidth. Furthermore, source adaptive bias networks is designed in the first stage and combined with a current-reused construction to acquire a compact chip size and maintain low power consumption. Then, the validation of design theory is implemented by employing a 0.15-µm gallium arsenide pseudomorphic high-electron-mobility transistor process. The measured results show that the proposed LNA achieves a small signal gain of 15.5–17.8 dB, a noise figure of 3–3.65 dB, and an output 1 dB compression point (OP1 dB) of 14.5–15.5 dBm from the target bandwidth of 2–18 GHz. In addition, the fabricated LNA consumes 220 mW from a 5 V supply and occupies a chip area of 1.2 × 1.5 mm2.

Cryogenic W-band Electron Spin Resonance Probehead with an Integral Cryogenic Low Noise Amplifier

The quest to enhance the sensitivity of electron spin resonance (ESR) is an ongoing challenge. One potential strategy involves increasing the frequency, for instance, moving from Q-band (approximately 35 GHz) to W-band (approximately 94 GHz). However, this shift typically results in higher transmission and switching losses, as well as increased noise in signal amplifiers. In this work, we address these shortcomings by employing a W-band probehead integrated with a cryogenic low-noise amplifier (LNA) and a microresonator. This configuration allows us to position the LNA close to the resonator, thereby amplifying the acquired ESR signal with minimal losses. Furthermore, when operated at cryogenic temperatures, the LNA exhibits unparalleled noise levels that are significantly lower than those of conventional room temperature LNAs. We detail the novel probehead design and provide some experimental results at room temperature as well as cryogenic temperatures for representative paramagnetic samples. We find, for example, that spin sensitivity of ~ 3 × 105 spins/√Hz is achieved for a sample of phosphorus doped 28Si, even for sub-optimal sample geometry with potential improvement to < 103 spins/√Hz in more optimal scenarios.

High‐Q LNA With a VCO for Small Calibration Frequency Errors

ABSTRACTA high‐quality (Q) low‐noise amplifier (LNA) combined with a voltage‐controlled oscillator (VCO) is presented for small frequency errors in self‐calibration. The proposed new double capacitive‐cross‐coupled structure controls negative impedance and thus, changes the working mode between the LNA and VCO with a small variation of parasitic capacitance, which results in a small calibration frequency error. High‐Q and low‐noise performances were theoretically analyzed and confirmed by simulation and measurement. The measured LNA operated from 2.2 to 2.44 GHz with a Q‐factor of 34 while the frequency offset was less than 0.9%. A power gain of 27 dB, noise figure of 2.1 dB, and input third‐order intercept point (IIP3) of −17 dBm were obtained while the power dissipations of the LNA and VCO modes were 10.2 and 4.7 mW from a 1.5‐V supply, respectively.

Design of CMOS low noise amplifier with inductive degeneration for navigation application

Abstract This paper presents an advanced Low Noise Amplifier (LNA) tailored for high-precision navigation applications, designed using the 180nm technology node and implemented in Cadence Virtuoso. The LNA features a single-ended amplifier configuration with cascaded NMOS transistors to achieve superior isolation and input matching through source degeneration, optimizing gain and noise performance. At 1.2 GHz, the amplifier achieves a gain of 33 dB and a noise figure of 1.3 dB. It demonstrates a 1 dB compression point of –16 dBm and a third-order intercept point (IIP3) of –10 dBm, with a power consumption of 44 mW from a 1.8 V supply. Post-layout simulations reflect a noise figure of 2.9 dB and a gain of 19.5 dB, highlighting practical design considerations. The layout area is 0.51 mm², underscoring the compact yet highly efficient design.

A Time-over-Threshold asynchronous front-end in 28 nm CMOS for the readout of pixel detectors in extreme radiation environments

This work describes the design, in a 28 nm CMOS technology, of a front-end channel for the readout of pixel sensors in future particle accelerators. The channel being developed leverages the Time-Over-Threshold technique for the numerical conversion of the detector signal amplitude, and includes a low-noise charge sensitive amplifier featuring a compact gain stage architecture. The front-end circuit features an equivalent noise charge not exceeding 70 electrons r.m.s. for a detector capacitance of 50 fF, with a threshold dispersion of the order of 20 electrons r.m.s. A prototype chip including a matrix of 8x32 readout channels has been submitted for fabrication. The design of the front-end channel, together with the main simulation results, is discussed in the paper.

Transimpedance amplifier for LGAD noise measurements: design and characterization

A wideband low-noise transimpedance amplifier (TIA) is designed for the measurement of the noise power spectral density (NPSD) of the current of low-gain avalanche diodes (LGADs). The design focuses on minimization of system background noise and maximization of operating bandwidth. The diffusive line effect of the high value resistor used in the feedback network has been analyzed, and a compensation of its effect has been implemented. With a transimpedance of 200 MΩ, a background white noise of 9.5 fA/√(Hz) and an input current dynamic range up to 20 nA are achieved. The useful bandwidth ranges from 1 kHz up to 3 MHz depending on the noise level to be measured. An effective method for calibrating the system and measuring its transfer function with high accuracy over the full bandwidth is described. The designed TIA enables an accurate characterization of LGADs noise, which is a crucial step for the technology qualification and for the prediction of the performance of these devices as radiation and particle detectors.

A Ku-Band Fully Differential Low-Power High-Input P1dB Low-Noise Amplifier.

This paper introduces a Ku-band fully differential low-power high-input 1 dB compression point (P1dB) low-noise amplifier (LNA). A fully differential structure is employed to enhance the input P1dB, common-mode noise rejection, and second harmonic cancellation. The first stage adopts large transistors and is optimized for power consumption and noise figure (NF). The output stage is designed with class AB bias, resulting in improved P1dB, power consumption, and linearity. The proposed two-stage fully differential common-source (CS) LNA was implemented using 65 nm bulk complementary metal oxide semiconductor (CMOS) technology. The fabricated LNA achieved a minimum NF of 2.7 dB at 13.6 GHz. Furthermore, it achieved a maximum gain of 19.92 dB at 12.2 GHz. Additionally, the LNA has an input P1dB of -7.45 dBm and an output power 1 dB compression point (OP1dB) of 10.09 dBm, both measured at 15.6 GHz. The LNA operates with a power consumption of 11 mW at a 1 V supply, and occupies a core size of 0.75 mm × 0.35 mm.

Designing common-source low noise amplifier utilizing GaN HEMT for sub-6 GHz in 5G wireless applications

Designing common-source low noise amplifier utilizing GaN HEMT for sub-6 GHz in 5G wireless applications

Analysis and Design of Low-Noise Radio-Frequency Power Amplifier Supply Modulator for Frequency Division Duplex Cellular Systems

This paper describes an analysis of power supply rejection and noise improvement techniques for an envelope-tracking power amplifier. Although the envelope-tracking technique improves efficiency, its power supply rejection ratio is much lower than that of average power tracking or a fixed-supply power amplifier. In FDD systems with the envelope-tracking technique, the low power supply rejection ratio generates much output noise in the RX band and degrades the receiver’s sensitivity. An SM is designed by using a 130 nm CMOS process, and the chip die area is 2 × 2 mm2 with a 25-pin wafer-level chip-scale package. The designed SM achieved peak efficiencies of 78–83% for LTE signals with a 5.8 dB PAPR and various channel bandwidths. For the low-output-noise-supply modulator, noise reduction techniques using resonant-frequency tuning and a notch filter are employed, and the measured results show maximum 1.8/5/5.3/3.8/3 dB noise reduction in LTE bands B17/B5/B2/B3/B7, respectively.

A 7.3–14.2 GHz 6.3 mW LNA with 9.4±0.6 dB gain using transformer feedback and peak-gain distribution

This article presents a wideband low-noise amplifier (LNA) with low power consumption and flat gain, implemented in a 180 nm CMOS technology. This LNA uses low voltage operation and current-reuse technology to reduce power consumption, and its cascaded structure is composed of a common-source (CS) stage with gate-source transformer feedback and a cascode stage. The T-coil structure is employed for inter-stage and output matching to expand bandwidth and adjust peak gain, while achieving in-band flat gain through the peak gain distribution technology. Measured results show that the LNA achieves a flat gain of 9.4 ± 0.6 dB over the 7.3–14.2 GHz frequency band, with a 3 dB bandwidth of 6.3–14.6 GHz and an in-band noise figure (NF) of lower than 4.2 dB. The core chip area is 0.29 mm2, and the power consumption is only 6.3 mW.

Stability and Matching Techniques on Microwave Amplifier using Inhomogeneous Dielectric Resonator: Preliminary Study

Stability and matching techniques on microwave amplifier have been an important consideration to maintain the required performances, such as high power for the high-power amplifier and low noise for low noise amplifier. Simultaneously, the issues of the stability need more attention to avoid the presence of the oscillations. Typically, the stability factor and matching components of the microwave amplifier are frequency dependent. Thus, a frequency tunable mechanism is required to ascertain that frequency of the microwave amplifier resides within the stable region. The dielectric resonator is incorporated as the frequency tunable mechanism that implemented to overcome this issue. The characteristics of the dielectric resonator are evaluated on their physical parameter and material with different topologies of the parallel microstrip lines. This includes the spacing and curves configuration and the orientation of angular position for the dielectric resonator, especially for the multi-permittivity dielectric resonator. Regarding the preliminary study, the angular position of the multi-permittivity dielectric resonator does not influence the stability performances of microwaves amplifier, especially on the resonant frequency. The obtained best configuration of proposed dielectric resonator is consisting of 155-degree curves configuration with 19 mm spacing between the parallel microstrip lines for same waveguide port position. This configuration of the proposed dielectric resonator is incorporated as stability element and matching components that known as dielectric matching for conditional stable and unconditional stable transistors at 5 GHz.

Miniaturized millimeter-wave dual-band band-pass on-chip filter in 0.13-μm SiGe BiCMOS

A design approach for a compact on-chip millimeter wave (mm-wave) dual-passband filter employing hybrid electromagnetic coupling (HEMC) and tunable transmission zeros (TZs) is presented in a 0.13-μm SiGe BiCMOS technology. A dual-mode double-layer series folded resonator with a quarter wavelength has been designed, which reduces the chip area by approximately 40 % compared to a single-mode planar quarter resonator. Additionally, TZs controlled by HEMC are introduced to enhance filter selectivity. A dual-passband filter operating in the W/F-band was realized in the 0.13-μm SiGe (Bi)-CMOS technology, with corresponding fractional bandwidths (FBW) of 15.1 % and 16.2 %, at 94/120 GHz respectively, and the average roll off rate of the filter is greater than 2 dB/GHz. The measured results demonstrate insertion losses below 5.7 dB in both passbands and the compact chip dimension is 626 × 813 μm2. When this chip can be placed after the low-noise amplifier in a receiver, the insertion loss has little negative impact on system performance. To our knowledge, this is the first time a 94/120 GHz dual-band BPF in Bi-CMOS technology has been implemented in such a small size. This study presents an alternative design methodology for miniaturizing and streamlining the structure of millimeter-wave dual-passband filters in the SiGe process.