Low-level Architecture Research Articles

Toward Patient-Centric Healthcare Systems: Key Requirements and Framework for Personal Health Records Based on Blockchain Technology

Healthcare data are considered sensitive and confidential, and storing these sensitive data in traditional (i.e., centralized) databases may expose risks, such as penetration or data leaks. Furthermore, patients may have incomplete health records since they visit various healthcare centers and leave their data scattered in different places. One solution to resolve these problems and permit patients to own their records is a decentralized personal health record (PHR); this can be achieved through decentralization and distribution systems, which are fundamental attributes of blockchain technology. Additionally, the requirements for this solution should be identified to provide practical solutions for stakeholders. This study aims to identify the key requirements for PHRs. A design science methodology was utilized to meet the study objectives, and thirteen healthcare experts were interviewed to elicit the requirements and the previous studies. Thirty-three requirements are defined, and based on these, high- and low-level architectures are developed and explained. The result illustrates that the developed solution-based Hyperledger Fabric framework is a promising method for the achievement of PHRs that guarantee security aspects, such as integrity, confidentiality, privacy, traceability, and access control.

MoCLORA—An Architecture for Legged-and-Climbing Modular Bio-Inspired Robotic Organism

MoCLORA (Modular Climbing-and-Legged Robotic Organism Architecture) is a software framework for climbing bio-inspired robotic organisms composed of modular robots (legs). It is presented as a modular low-level architecture that coordinates the modules of an organism with any morphology, at the same time allowing exchanges between the physical robot and its digital twin. It includes the basic layers to control and coordinate all the elements, while allowing adding new higher-level components to improve the organism's behavior. It is focused on the control of both the body and the legs of the organism, allowing for position and velocity control of the whole robot. Similarly to insects, which are able to adapt to new situations after the variation on the capacity of any of their legs, MoCLORA allows the control of organisms composed of a variable number of modules, arranged in different ways, giving the overall system the versatility to tackle a wide range of tasks in very diverse environments. The article also presents ROMERIN, a modular climbing and legged robotic organism, and its digital twin, which allows the creation of different module arrangements for testing. MoCLORA has been tested and validated with both the physical robot and its digital twin.

Evaluating MPI resource usage summary statistics

The Message Passing Interface (MPI) remains the dominant programming model for scientific applications running on today’s high-performance computing (HPC) systems. This dominance stems from MPI’s powerful semantics for inter-process communication that has enabled scientists to write applications for simulating important physical phenomena. MPI does not, however, specify how messages and synchronization should be carried out. Those details are typically dependent on low-level architecture details and the message characteristics of the application. Therefore, analyzing an application’s MPI resource usage is critical to tuning MPI’s performance on a particular platform. The result of this analysis is typically a discussion of the mean message sizes, queue search lengths and message arrival times for a workload or set of workloads. While a discussion of the arithmetic mean in MPI resource usage might be the most intuitive summary statistic, it is not always the most accurate in terms of representing the underlying data. In this paper, we analyze MPI resource usage for a number of key MPI workloads using an existing MPI trace collector and discrete-event simulator. Our analysis demonstrates that the average, while easy and efficient to calculate, is a useful metric for characterizing latency and bandwidth measurements, but may not be a good representation of application message sizes, match list search depths, or MPI inter-operation times. Additionally, we show that the median and mode are superior choices in many cases. We also observe that the arithmetic mean is not the best representation of central tendency for data that are drawn from distributions that are multi-modal or have heavy tails. The results and analysis of our work provide valuable guidance on how we, as a community, should discuss and analyze MPI resource usage data for scientific applications.

5G network slice for digital real-time healthcare system powered by network data analytics

In the wake of the COVID-19 pandemic, where almost the entire global healthcare ecosystem struggled to handle patients, it’s evident that the healthcare segment needs a virtual real-time digital support system. The recent advancements in technology have enabled machine-to-machine communication, enhanced mobile broadband, and real-time biometric data analytics. These could potentially fulfill the requirements of an end-to-end digital healthcare system. For building such a system, there is also a need for a dedicated and specialized communication network. Such a system will not only support dynamic throughput, latency and payload but also provide guaranteed QoS (Quality of Service) at every instant. The motive of our study was to define an implementable low-level architecture for the digital healthcare system by using the 5G Network Slice that incorporates all these features. Best-in-class wearable devices will collect the biometric data and transmit it via the 5G network slice. Data analytics is then applied to the collected data to build a knowledge graph used for quick predictions and prescriptions. The architecture also keeps in mind the security and integrity aspects of healthcare data.

PORTING ARDUPILOT TO ESP32: TOWARDS A UNIVERSAL OPEN-SOURCE ARCHITECTURE FOR AGILE AND EASILY REPLICABLE MULTI-DOMAINS MAPPING ROBOTS

Abstract. In this article, we are interested in the implementation of an open-source low-level architecture (critical system) adapted to agile and easily replicable close-range remote sensing robots operating in multiple evolution domains. After reviewing the existing autopilots responding to these needs, we discuss the available hardware solutions and their limits. Then, we propose an original solution (software and hardware) that we developed to obtain a universal low-level architecture for all our exploration robots, whatever their environment of evolution, and the steps needed to make it run on our chosen family of micro-controllers: the ESP32. Finally, we present the operational results obtained on our different platforms (land, surface, submarine and air), their limits and the envisaged perspectives.

Multi-Agent Modeling of Cyber-Physical Systems for IEC 61499 Based Distributed Automation

The traditional industrial automation systems developed under IEC 61131-3 in centralized control are statically programmed with determined procedures to perform predefined behaviors/tasks in structured environments. A major challenge for the traditional system is the frequent changes and constant uncertainties of the system itself, its operations and the operating environments. Therefore, in this paper we are trying to develop a two-layer architecture for modelling industrial cyber-physical systems, in which the multi-agent computing model is designed for the high-level architecture and the IEC 61499 function block model is applied for the low-level architecture. It aims to integrate system intelligence by communicating and computing cores from the high-level cyber modules and real-time adaptation by distributed and intelligent control of the low-level physical modules. The proposed modeling framework is tested for the feasibility study through preliminary experiments on Jetson Nano and Raspberry Pi by using agent modeling tool SPADE and function block modeling tool Eclipse 4diac.

SIMD programming using Intel vector extensions

Single instruction multiple data (SIMD) extensions are one of the most significant capabilities of recent General Purpose Processors (GPPs) which improves the performance of applications with less hardware modification. Each GPP vendor such as HP, Sun, Intel, and AMD has its particular Instruction Set Architecture (ISA) and SIMD micro-architecture with different perspectives. Intel expanded SIMD technologies from hardware and software point of view. It has introduced SIMD technologies such as MultiMedia eXtensions (MMX), Streaming SIMD Extensions (SSE), Advanced Vector eXtensions (AVX), Fused Multiply Add (FMA) and AVX-512 sets. During micro-processors developments path, register width has been extended from 64 bits to 512 bits and number of vector registers has been increased from 8 to 32. Wider registers provide more parallelism ways and more registers reduce extra data movement to the cache memory. In order to gain the advantages of SIMD extensions, many programming approaches have been developed. Compiler Automatic Vectorization (CAV) as an implicit vectorization approach, provides simple and easy SIMDization tools. While, performance improvement of CAV is not always granted, most compilers auto-vectorize simple loops. On the other hand, for explicit vectorization, Intrinsic Programming Model (IPM) provides low-level access to vector registers for SIMDizing. However, programming with IPM requires great amount of expertise especially in low-level architecture feature, thus, choosing the suitable instructions and vectorization methodology for mapping to a certain algorithm is important. Moreover, portability, compatibility, scalability and compiler optimization might limit the advantage of IPM. Our goal in this paper is as follows. First, we provide a review of SIMD technology in general and Intel’s SIMD extensions in particular. Second, some SIMD features of Intel SIMD technologies, MMX, SSEs, AVX, and FMA in terms of ISA, vector width, and SIMD programming tools are comparatively discussed. Third, in order to compare the performance of different auto-vectorizers and IPM approaches using Intel C++ compiler (ICC), GNU Compiler Collection (GCC) and Low Level Virtual Machine (LLVM), we map and implement some representative multimedia kernels on AVX and AVX2 extensions. Finally, our experimental results show that although the performance improvement using IPM approach is higher than CAVs, programmer needs more programming efforts and knows different mapping strategists. Therefore, extending auto-vectorizers abilities to generate more efficient vectorized codes is an important issue in different compilers.

Formally verifying exceptions for low-level code with separation logic

Exceptions in low-level architectures are implemented as synchronous interrupts: upon the execution of a faulty instruction the processor jumps to a piece of code that handles the error. Previous work has shown that assembly programs can be written, verified and run using higher-order separation logic [14]. However, execution of faulty instructions is then specified as either being undefined or terminating with an error. In this paper, we study synchronous interrupts and show their usefulness by implementing a memory allocator. This shows that it is indeed possible to write positive specifications of programs that fault. All of our results are mechanised in the interactive proof assistant Coq.

Parallel Implementation of the Recursive Least Square for Hyperspectral Image Compression on GPUs

Compression is a very important technique for remotely sensed hyperspectral images. The lossless compression based on the recursive least square (RLS), which eliminates hyperspectral images` redundancy using both spatial and spectral correlations, is an extremely powerful tool for this purpose, but the relatively high computational complexity limits its application to time-critical scenarios. In order to improve the computational efficiency of the algorithm, we optimize its serial version and develop a new parallel implementation on graphics processing units (GPUs). Namely, an optimized recursive least square based on optimal number of prediction bands is introduced firstly. Then we use this approach as a case study to illustrate the advantages and potential challenges of applying GPU parallel optimization principles to the considered problem. The proposed parallel method properly exploits the low-level architecture of GPUs and has been carried out using the compute unified device architecture (CUDA). The GPU parallel implementation is compared with the serial implementation on CPU. Experimental results indicate remarkable acceleration factors and real-time performance, while retaining exactly the same bit rate with regard to the serial version of the compressor.

High-Level Synthesis Optimization for Blocked Floating-Point Matrix Multiplication

In the last decade floating-point matrix multiplication on FPGAs has been studied extensively and efficient architectures as well as detailed performance models have been developed. By design these IP cores take a fixed footprint which not necessarily optimizes the use of all available resources. Moreover, the low-level architectures are not easily amenable to a parameterized synthesis. In this paper high-level synthesis is used to fine-tune the configuration parameters in order to achieve the highest performance with maximal resource utilization. An\ exploration strategy is presented to optimize the use of critical resources (DSPs, memory) for any given FPGA. To account for the limited memory size on the FPGA, a blockoriented matrix multiplication is organized such that the block summation is done on the CPU while the block multiplication occurs on the logic fabric simultaneously. The communication overhead between the CPU and the FPGA is minimized by streaming the blocks in a Gray code ordering scheme which maximizes the data reuse for consecutive block matrix product calculations. Using highlevel synthesis optimization, the programmable logic operates at 93% of the theoretical peak performance and the combined CPU-FPGA design achieves 76% of the available hardware processing speed for the floating-point multiplication of 2K by 2K matrices.

Parallel Spatial–Spectral Hyperspectral Image Classification With Sparse Representation and Markov Random Fields on GPUs

Spatial-spectral classification is a very important topic in the field of remotely sensed hyperspectral imaging. In this work, we develop a parallel implementation of a novel supervised spectral-spatial classifier, which models the likelihood probability via l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> - l <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> sparse representation and the spatial prior as a Gibbs distribution. This classifier takes advantage of the spatial piecewise smoothness and correlation of neighboring pixels in the spatial domain, but its computational complexity is very high which makes its application to time-critical scenarios quite limited. In order to improve the computational efficiency of the algorithm, we optimized its serial version and developed a parallel implementation for commodity graphics processing units (GPUs). Our parallel spatial-spectral classifier with sparse representation and Markov random fields (SSC-SRMRF-P) exploits the low-level architecture of GPUs. The parallel optimization of the proposed method has been carried out using the compute unified device architecture (CUDA). The performance of the parallel implementation is evaluated and compared with the serial and multicore implementations on central processing units (CPUs). In fact, the proposed method has been designed to adequately exploit the massive data parallel capacities of GPUs together with the control and logic capacities of CPUs, thus resorting to a heterogeneous CPU-GPU framework in the design of the parallel algorithm. Experimental results using real hyperspectral images demonstrate very high performance for the proposed CPU-GPU parallel method, both in terms of classification accuracy and computational performance.

Low-Level Flexible Architecture with Hybrid Reconfiguration for Evolvable Hardware

Field-programmable gate arrays (FPGAs) can be considered to be the most popular and successful platform for evolvable hardware. They allow one to establish and later reconfigure candidate solutions. Recent work in the field of evolvable hardware includes the use of virtual and native reconfigurations. Virtual reconfiguration is based on the change of functionality by hardware components implemented on top of FPGA resources. Native reconfiguration changes the FPGA resources directly by means provided by the FPGA manufacturer. Both of these approaches have their disadvantages. The virtual reconfiguration is characterized by lower maximal operational frequency of the resulting solutions, and the native reconfiguration is slower. In this work, a hybrid approach is used merging the advantages while limiting the disadvantages of the virtual and native reconfigurations. The main contribution is the new low-level architecture for evolvable hardware in the new Zynq-7000 all-programmable system-on-chip. The proposed architecture offers high flexibility in comparison with other evolvable hardware systems by considering direct modification of the reconfigurable resources. The impact of the higher reconfiguration time of the native approach is limited by the dense placement of the proposed reconfigurable processing elements. These processing elements also ensure fast evaluation of candidate solutions. The proposed architecture is evaluated by evolutionary design of switching image filters and edge detectors. The experimental results demonstrate advantages over the previous approaches considering the time required for evolution, area overhead, and flexibility.

System Integration for Real-Time Mobile Manipulation

Mobile manipulators are one of the most complicated types of mechatronics systems. The performance of these robots in performing complex manipulation tasks is highly correlated with the synchronization and integration of their low-level components. This paper discusses in detail the mechatronics design of a four wheel steered mobile manipulator. It presents the manipulator's mechanical structure and electrical interfaces, designs low-level software architecture based on embedded PC-based controls, and proposes a systematic solution based on code generation products of MATLAB and Simulink. The remote development environment described here is used to develop real-time controller software and modules for the mobile manipulator under a POSIX-compliant, real-time Linux operating system. Our approach enables developers to reliably design controller modules that meet the hard real-time constraints of the entire low-level system architecture. Moreover, it provides a systematic framework for the development and integration of hardware devices with various communication mediums and protocols, which facilitates the development and integration process of the software controller.

Area-Delay Estimation by Concurrent Optimization of FPGA Architecture Parameters using Geometric Programming

paper presents the application of geometric programming for combined high-level and low-level architecture parameter exploration. This paper builds an geometric programming framework for reconfigurable architectures, and presents a full delay and area model of an FPGA. This optimization allows high-level architectural parameter selection and the transistor sizing to be done concurrently. The transistor values are derived using 45nm predictive technology model. CVX framework for MATLAB is used to run the geometric programming framework. The area and critical path delay are determined for given cost function by single-stage and multi- stage approach.

I3WSN: Industrial Intelligent Wireless Sensor Networks for indoor environments

Sensor Web Enablement (SWE) technologies have been successfully applied to a great variety of outdoor scenarios but, in practical terms, little effort has been applied for indoor environments, and even less in the field of industrial applications. This article presents an intelligent SWE application for an indoor and industrial scenario, with the aim of improving and increasing the levels of human safety. The base low-level architecture is built on top of wireless sensor networks (WSN) connected to a Sensor Observation Service (SOS). Higher layers in the architecture include services that make real time decisions based on the collected data. Both simulation and experimental results are presented. The paper shows the viability of our approach in terms of performance, scalability, modularity and safety.

Difficulties learning computer architecture

During a course on computer architecture, assembler, C programming, network and communication, 57 out of 300 students were followed closely by questionnaires and tests in order to evaluate their learning of computer architecture. The results indicate both that the students' understanding of logic gates and Boolean algebra is poorer than preferred, and that the students also have difficulties grasping the implementation of higher level constructs in low level architecture features. Better results might have been achieved if the teaching of architecture was closely linked to the students' previous training in programming.

Telerobotic Training System Through the Web: Low Level Architecture

The paper gives an overview description of a web based telerobotic training system that allows students to practice the classroom theoretical concepts with a virtual 3D robotics environment as well as a real robot. Then, it focuses on the low level architecture, the way the system is organized into several modules and the communication procedure through the CORBA standard. The user interface is implemented using JAVA, and the interaction with the robot is accomplished through a JAVA 3D virtual and augmented reality environment, as well as a simplification of the natural language. The paper describes the way the user interface can be used in order to manipulate objects over a board using the virtual and augmented reality interface.

Internet access to a home area network

The AutoHan project implements a self-configuring software architecture for home area networks that offers an XML-based registry and HTTP-based service. The article begins by introducing the low-level architectures of the AutoHan project that enable different networking technologies to interoperate and define one logical IP network. It then describes the two core services that enable resources to export, discover and interoperate with AutoHan by using these low-level architectures. Finally, the article discusses naming and addressing issues for Internet access and shows how XML and HTTP allowed extension of the system to support Internet access through IHan (Internet home area network).

Design and implementation of a real-time holonic control system for manufacturing

This paper describes a new approach to low-level process/machine control for manufacturing that is based on the holonic manufacturing systems (HMSs) paradigm. The primary motivation for this work is the requirement for manufacturing systems that can automatically and intelligently adapt to changes in the manufacturing environment while still achieving overall system goals. To meet this requirement, a low-level architecture for distributed process/machine control is described that is dynamically reconfigurable and supports distributed applications based on the IEC-1499 function block (FB) standard. To evaluate the feasibility of this new approach, a prototype system based on this architecture is described and performance results are reported.

Digit Pipelined Arithmetic for 3-D Massively Parallel Optoelectronic Circuits

A concept for a future integer arithmetic unit suitable for a realization with 3-D optoelectronic very large scale integrated (VLSI) circuits is presented. Due to the use of optical interconnections running vertically to the circuit's surface no pin limitation is given. This allows massively parallelism and a higher throughput performance than in all-electronic solutions. To exploit the potential of optical interconnections in VLSI systems efficiently well-adapted low-level algorithms and architectures have to be developed. This is demonstrated for a pipelined arithmetic unit using a redundant number representation. A transistor layout for the optoelectronic circuits is given as well as a specification for the necessary optical interconnection scheme linking the circuits with free-space optics. It is shown that the throughput can be increased by a factor of 10 to 50 compared to current all-electronic processors by considering state-of-the-art optical and optoelectronic technology. Furthermore we present results we gained by investigations on a first realized optoelectronic VLSI test chip.