Low Leakage Current Level Research Articles

Metallorganic Chemical Vapor Deposition of TaOx N y as a High-Dielectric-Constant Material for Next-Generation Devices

Tantalum oxynitride films were deposited by metallorganic chemical vapor deposition. Pentaethoxytantalum the most widely used source gas for depositing was used as the source gas and as the reaction gas. The activation energy of the surface reaction was estimated to be 1.1 eV for a single-source deposition deposition), and to decrease to ca. 0.37 eV with the addition of over 50 sccm Deposition rate at the surface-reaction-controlled regime increased to 2.6 nm/min with 100 sccm but decreased upon adding more than 100 sccm of The overall deposition rate of the surface-reaction-controlled regime was as predicted by the Langmuir-Hinshelwood model. With an increase in both deposition temperature and flow rate, the TaON phase predominated over The dielectric constants of the as-deposited and -annealed films were 51 and 146, respectively. It is believed that films are attractive high-dielectric-constant materials for the next generation of gigabit dynamic random access memory devices. However, films exhibit relatively high current leakage densities of to at 1.0 MV/cm. A porous film microstructure was observed by transmission electron microscopy, and this seemed to be responsible for these high leakage currents. Further systematic optimization of the deposition and annealing processes is needed to produce a dense microstructure with a low leakage current level. © 2002 The Electrochemical Society. All rights reserved.

Electrical characteristics of a TaOxNy/ZrSixOy stack gate dielectric for metal–oxide–semiconductor device applications

In this letter, we describe a process for the preparation of high-quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional chemical oxide and nitride as interfacial layers, TaOxNy metal–oxide–semiconductor capacitors using ZrSixOy as an interfacial layer exhibit lower leakage current levels at the same oxide thickness and a lower interface state density. We were able to confirm the TaOxNy/ZrSixOy stack structure by Auger electron spectroscopy and transmission electron microscopy analyses. Zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.

Silicon drift detectors for high count rate X-ray spectroscopy at room temperature

Silicon Drift Detectors (SDDs) combine a large sensitive area with a small value of the output capacitance and are therefore well suited for high resolution, high count rate X-ray spectroscopy. The low leakage current level obtained by the elaborated processing technology makes it possible to operate them at room temperature or with moderate cooling. A brief description of the device principle is followed by the presentation of first results of a new production of large area SDDs with external electronics. Performance and applications of the already established SDDs with on-chip amplification are summarised. Various shapes of Multichannel Drift Detectors are introduced as well as their use in new experiments like X-ray holography and in new systems like an Anger camera for γ-ray imaging.

Electrical Characteristics of TaOxNy/ZrSixOy Stack Gate Dielectric for MOS Device Applications

ABSTRACTThis letter describes a unique process for the preparation of high quality tantalum oxynitride (TaOxNy) with zirconium silicate (ZrSixOy) as an interfacial layer for use in gate dielectric applications. Compared with conventional native silicon oxide and oxynitride as an interfacial layer, tantalum oxynitride (TaOxNy) MOS capacitors using zirconium silicate (ZrSixOy) as an interfacial layer exhibit lower leakage current levels at the same equivalent oxide thickness. We were able to confirm TaOxNy/ZrSixOy stack structure by auger electron spectroscopy (AES) and transmission electron microscope (TEM) analysis. The estimated dielectric constant of TaOxNy and ZrSixOywere approximately 67 and 7, respectively. The zirconium silicate is a promising interfacial layer for future high-k gate dielectric applications.

Novel Barrier Dielectric Liner Prepared by Liquid-Phase Deposition and NH3-Plasma Annealing

A novel barrier dielectric liner prepared by liquid-phase deposition and post-deposition NH3-plasma annealing is proposed as a capping layer to be used on damascene trenches of low-permittivity dielectric. The liner technology meets the essential requirements such as (1) thin and conformal deposition, (2) a low leakage current level, and (3) effective blocking of Cu penetration. With this barrier dielectric liner, Cu damascene interconnection is expected to have a low leakage current and high resistance to Cu penetration into the low-permittivity dielectrics even if the barrier metal fails locally.

Leakage current patterns on contaminated polymeric surfaces

This paper presents measurements of low-level leakage current (LC) patterns on naturally aged insulators and artificially contaminated material samples as well as insulaton. A nonlinear behaviorof the LC has been observed. Possible causes for this behavior are discussed and its relations to surface hydrophobicity and electric stress are described. In addition, neural networks are trained to recognize the LC patterns as well as to estimate their harmonic contents.

Thermally robust Ta/sub 2/O/sub 5/ capacitor for the 256-Mbit DRAM

The thermal degradation of the Ta/sub 2/ O/sub 5/ capacitor during BPSG reflow has been studied. The cause of deterioration of Ta/sub 2/O/sub 5/ with the TiN top electrode was found to be the oxidation of TiN. By placing a poly-Si layer between TiN and BPSG to suppress oxidation, the low leakage current level was maintained after BPSG reflow at 850/spl deg/C. The Ta/sub 2/O/sub 5/ capacitor with the TiN/poly-Si top electrode was integrated into 256-Mbit DRAM cells and excellent leakage current characteristics were obtained.

A hot hole-induced low-level leakage current in thin silicon dioxide films

A new kind of stress-induced low-level leakage current (LLLC) in thin silicon dioxide is reported. It is observed after the stress of hot hole injection at the gate edge. Since voltage dependence of this new kind of LLLC is steeper than that of conventional FN stress-induced LLLC, each conduction mechanism may be different. This LLLC is reduced by both hot electron injection and UV irradiation. These reductions are never observed in FN stress-induced LLLC. The most promising mechanism is sequential tunneling via trapped holes.

The charging and discharging of high-voltage stress-generated traps in thin silicon oxide

Excess high-voltage stress-generated low-level leakage currents through 10 nm silicon oxides, previously described as DC currents, are shown to decay to the limit of detection given adequate observation time and, thus, have no discernible component. A physical model is presented which describes the majority of the excess low-level leakage currents in terms of the charging and discharging of traps previously generated by the high voltage stress. Excess low-level leakage currents measured with voltage pulses with polarity opposite to that of the stress voltage are found to contain an additional current component, which is explained by the transient charging and discharging of certain traps inside the oxide. Evidence is presented which suggests that an oxide trap generated by the high-voltage stress can contain either a positive or a negative charge, in addition to being neutral and that the traps are located near both oxide interfaces. All of the trap charging and discharging currents can be explained by the flow of electrons into and out of traps generated by the high voltage stress, without resorting to the flow of holes in the oxide.

The superposition of transient low-level leakage currents in stressed silicon oxides

Thin films of silicon oxide were stressed at high voltages, which generated traps inside of the oxides and at the oxide interfaces. The transient low-level leakage currents were measured in these stressed oxides as a function of the magnitude of low voltages applied after the stress. It was found that the transient low-level leakage currents resulting from the application of two voltage pulses of different magnitudes with no relaxation time between the pulses were the same as the linear superposition of the currents resulting from each pulse when measured separately. The linear superposition of these transient currents can result in currents which change polarity during the application of a constant voltage across the oxide. This bipolar current is due to the transient charging and discharging of stress generated traps, which are distributed in space and energy within the oxide.

Effects of nitrogen incorporation during growth on thin oxide wearout and breakdown

Thin oxides, 6.4–7.6 nm thick, have been formed in oxygen with varying levels of nitrogen incorporated into the oxidation ambient. In addition to films with no nitrogen, the nitrogen concentration was varied from 0.00001 to 10% in decade increments. The wearout and breakdown characteristics of these oxides were measured. Wearout was quantified by measuring the changes in the low-level leakage currents, the changes in the mid-gap interface trap densities, the shifts in the flat-band voltages, and the number of traps generated inside of the oxides, all by high voltage stresses. Breakdown was characterized by measuring the time-zero-breakdown voltage distributions. It was found that the wearout was independent of the nitrogen concentration but the breakdown voltages decreased as the nitrogen concentration increased. The average breakdown voltage dropped by |1 V| for oxides with 0.1% N 2 and by |3 V| for oxides with 10% N 2, with the number of low-voltage breakdowns also increasing as the nitrogen concentration increased. It was felt that the nitrogen was incorporated into the oxide both relatively uniformly throughout the oxide and in local non-uniform regions. The uniform distribution inside of the oxide did not affect the wearout properties of the oxide, which were determined by high-field, bond breaking of silicon-oxygen bonds. The regions with non-uniform concentrations of nitrogen introduced local asperities that affected the breakdown voltage distributions by generating local high field regions and locally high trap concentrations.

Dislocation free gate process using in situ doped polysilicon thin films by crystallization-induced stress of the films

In situ doped polysilicon thin films have been found useful for half-micron technology because the film deposition process is simple and the film surface is rather flat. The characteristics of the film are evaluated experimentally to apply it to a gate electrode material. It is confirmed that the film has much better tolerance to HF penetration than the conventional POCl/sub 3/-treated polysilicon thin film, and has good surface flatness. However, abnormal leakage current is observed in MOSFETs using the in situ doped polysilicon gate, while the leakage current of the MOSFETs using the conventional POCl/sub 3/ treated polysilicon gate is low and stable. The abnormal leakage current is found to be caused by dislocations in the silicon substrate at the gate edges. The films must be annealed fully to eliminate dislocations at the gate edges, which results in a low and stable leakage current level of MOSFETs.

Stress Induced Increased Low Level Leakage in Thin Oxides

ABSTRACTIt has been observed that the low-level, pre-tunneling currents through thin gate oxides increased after the oxides had been stressed at high voltages. The number of traps inside of the oxide generated by the stress has been shown to increase as the 1/3 power of the fluence that had passed through the oxide during the stress. The increases in the low-level, pre-tunneling currents have been shown to be proportional to the number of stress generated traps in the oxide and not to the fluence during the stress. The voltage dependences of the excess low-level leakage currents were stress and measurement polarity dependent. Attempts have been made to fit the voltage dependences of the excess low-level currents to Fowler-Nordheim tunneling, Frenkel-Poole conduction or Schottky barrier lowering. The increase in the portion of the low-level, pre-tunneling current that was not dependent on stress/measurement polarity sequence was best fit using Schottky emission currents. The model that has been developed to describe the increases in the low-level currents has centered on trap-assisted currents through the oxides.

An evaluation of FUROX isolation technology for VLSI/nMOSFET fabrication

A defect-free near-zero bird's beak, fully recessed oxide (FUROX) field-isolation technology has been evaluated through the fabrication of VLSI/nMOSFETs. The FUROX process mainly consists of: (1) a thin nitrided oxide as the stress buffer layer and the interface sealing layer for local oxidation enhancement; and (2) a novel more-reliable nitride masking structure for a two-step field oxidation and a self-aligned field implantation. The elimination of the necking effect on positive photoresist and the improvement of critical dimension control for polysilicon gates using the planarized isolation have been demonstrated. Through electrical characterization of n/sup +/-p diodes and field and active transistors, the FUROX devices have been shown to provide low leakage-current level, good isolation property, and large recovery of the effective channel width (1.4 mu m). Therefore, the serious narrow-width effects that exist in conventional LOCOS (local oxidation of silicon) isolated have been effectively reduced. Using histogram analysis, the reliability of the masking structure had hence good uniformity of device properties for FUROX isolation have been exhibited. The successful fabrication of FUROX devices with W/sub eff/=0.6 mu m clearly demonstrates that FUROX isolation technology is greatly superior to conventional LOCOS. >