Neuromorphic (NC) designs have gained significant interest in recent hardware research due to its low-power consumption. Low-power and low-latency router design is one of the most critical component to ensure NC hardware's scalability and energy efficiency. Various router designs have been proposed to achieve high performance. However, this leads to complex router architectures and thus high area and power consumption. Furthermore, non-uniform traffic patterns of spiking neurons can cause network congestion and unnecessary power consumption. In this brief, we propose a congestion-aware routing algorithm to alleviate the congestion of routers in the middle and reduce network latency. Besides, a globally asynchronous, locally synchronous low-cost router architecture is deployed to relax the global clock tree constraint at chip level. Finally, a novel clock gating circuit is proposed to reduce the dynamic power consumption of routers. Our results show that averagely it reduces the router power consumption by more than 50%. The proposed router achieves ultra-low energy consumption of $2.3\times 10^{-2}$ pJ/bit and a small area of only 0.007 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .