Low-jitter Clock Generator Research Articles

A 2.56-GHz SEU Radiation Hard $LC$ -Tank VCO for High-Speed Communication Links in 65-nm CMOS Technology

This paper presents a radiation tolerant phase-locked loop CMOS application-specified integrated circuit with an optimized voltage controlled oscillator (VCO) for single-event upsets (SEUs). The circuit is designed for high-energy particle physics experiments for low-jitter clock generation and clock recovery. An optimal tuning strategy of the VCO is presented that minimizes the cross section and the SEU sensitivity of the oscillator. The circuit is processed in a 65-nm CMOS technology and has been irradiated with heavy ions with a linear energy transfer between 10 to 69.2 MeV.cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /mg. A comparison has been made with a conventional oscillator which proves a significant improvement in SEU sensitivity.

Design and Analysis of a 1.8-GHz Open-Loop Modulator for Phase Modulation and Frequency Synthesis Using TDC-Based Calibration

A nonlinearity calibration technique is proposed for an open-loop phase modulator (PM), for wideband phase modulation, and for multiple-output, low-jitter clock generation. The design considerations and key performance aspects of the calibration technique are discussed. The PM integrates a digital phase-locked loop, local oscillator distribution network, and digital calibration. A prototype was implemented in 0.13- $\mu \text{m}$ CMOS 1.8-GHz Gaussian frequency shift keying (GFSK) transmitter integrated circuit. Measurements on the prototype show that out-of-band quantization noise is 56 dB lower than that of the signal when transmitting 20-Mb/s GFSK signal and the rms error is only 3.2%. The power consumption of the PM is 18 mW. The measured spurious tones of the clock generation unit are below −46 dBc.

A Low-Jitter Area-Efficient LC-VCO Based Clock Generator in 0.13-.MU.m CMOS

This letter presents an ultra low-jitter clock generator that employs an area-efficient LC-VCO. In order to fully utilize the area of the on-chip inductor, the loop filter of a phase locked loop (PLL) is located underneath the inductor. A prototype chip implemented in 0.13µm CMOS process achieves 105MHz to 225MHz of clock frequency while consuming 4.2mW from 1.2V supply. The measured rms jitter and normalized rms jitter of the proposed clock generator are 2.8ps and 0.031% at 105MHz, respectively.